On Fri, Apr 30, 2021 at 3:40 PM Siew Chin Lim <elly.siew.chin....@intel.com> wrote: > > Add memory clock manager driver for N5X. Provides memory clock > initialization and enable functions. > > Signed-off-by: Siew Chin Lim <elly.siew.chin....@intel.com> > > --- > v2: > - common.h need to be included before clock_manager.h > - For consistency, use small letter fo 0x0c and 0x1c in macros > --- > drivers/clk/altera/Makefile | 1 + > drivers/clk/altera/clk-mem-n5x.c | 136 +++++++++++++++++++++++++++++++ > drivers/clk/altera/clk-mem-n5x.h | 84 +++++++++++++++++++ > 3 files changed, 221 insertions(+) > create mode 100644 drivers/clk/altera/clk-mem-n5x.c > create mode 100644 drivers/clk/altera/clk-mem-n5x.h >
[...] + > +/* Clock Manager registers */ > +#define MEMCLKMGR_STAT 4 > +#define MEMCLKMGR_INTRGEN 8 > +#define MEMCLKMGR_INTRMSK 0x0c > +#define MEMCLKMGR_INTRCLR 0x10 > +#define MEMCLKMGR_INTRSTS 0x14 > +#define MEMCLKMGR_INTRSTK 0x18 > +#define MEMCLKMGR_INTRRAW 0x1c > + > +/* Memory Clock Manager PPL group registers */ > +#define MEMCLKMGR_MEMPLL_EN 0x20 > +#define MEMCLKMGR_MEMPLL_ENS 0x24 > +#define MEMCLKMGR_MEMPLL_ENR 0x28 > +#define MEMCLKMGR_MEMPLL_BYPASS 0x2c > +#define MEMCLKMGR_MEMPLL_BYPASSS 0x30 > +#define MEMCLKMGR_MEMPLL_BYPASSR 0x34 > +#define MEMCLKMGR_MEMPLL_MEMDIV 0x38 > +#define MEMCLKMGR_MEMPLL_PLLGLOB 0x3c > +#define MEMCLKMGR_MEMPLL_PLLCTRL 0x40 > +#define MEMCLKMGR_MEMPLL_PLLDIV 0x44 > +#define MEMCLKMGR_MEMPLL_PLLOUTDIV 0x48 > +#define MEMCLKMGR_MEMPLL_EXTCNTRST 0x4c > + > +#define MEMCLKMGR_CTRL_BOOTMODE BIT(0) > + > +#define MEMCLKMGR_STAT_MEMPLL_LOCKED BIT(8) > + > +#define MEMCLKMGR_STAT_ALLPLL_LOCKED_MASK \ > + (MEMCLKMGR_STAT_MEMPLL_LOCKED) > + > +#define MEMCLKMGR_INTER_MEMPLLLOCKED_MASK 0x00000001 > +#define MEMCLKMGR_INTER_MEMPLLLOST_MASK 0x00000004 Use BIT() macro. > + > +#define MEMCLKMGR_BYPASS_MEMPLL_ALL 0x1 > + > +#define MEMCLKMGR_MEMDIV_MPFEDIV_OFFSET 0 > +#define MEMCLKMGR_MEMDIV_APBDIV_OFFSET 4 > +#define MEMCLKMGR_MEMDIV_DFICTRLDIV_OFFSET 8 > +#define MEMCLKMGR_MEMDIV_DFIDIV_OFFSET 12 > +#define MEMCLKMGR_MEMDIV_DFICTRLDIV_MASK 0x1 Use BIT() macro. > +#define MEMCLKMGR_MEMDIV_DIVIDER_MASK 0x3 Use GENMASK(). > + > +#define MEMCLKMGR_PLLGLOB_PSRC_MASK GENMASK(17, 16) > +#define MEMCLKMGR_PLLGLOB_PSRC_OFFSET 16 > +#define MEMCLKMGR_PLLGLOB_LOSTLOCK_BYPASS_EN_MASK BIT(28) > +#define MEMCLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK BIT(29) > + > +#define MEMCLKMGR_PSRC_EOSC1 0 > +#define MEMCLKMGR_PSRC_INTOSC 1 > +#define MEMCLKMGR_PSRC_F2S 2 > + > +#define MEMCLKMGR_PLLCTRL_BYPASS_MASK BIT(0) > +#define MEMCLKMGR_PLLCTRL_RST_N_MASK BIT(1) > + > +#define MEMCLKMGR_PLLDIV_DIVR_MASK GENMASK(5, 0) > +#define MEMCLKMGR_PLLDIV_DIVF_MASK GENMASK(16, 8) > +#define MEMCLKMGR_PLLDIV_DIVQ_MASK GENMASK(26, 24) > +#define MEMCLKMGR_PLLDIV_RANGE_MASK GENMASK(30, 28) > + > +#define MEMCLKMGR_PLLDIV_DIVR_OFFSET 0 > +#define MEMCLKMGR_PLLDIV_DIVF_OFFSET 8 > +#define MEMCLKMGR_PLLDIV_DIVQ_QDIV_OFFSET 24 > +#define MEMCLKMGR_PLLDIV_RANGE_OFFSET 28 > + > +#define MEMCLKMGR_PLLOUTDIV_C0CNT_MASK GENMASK(4, 0) > +#define MEMCLKMGR_PLLOUTDIV_C0CNT_OFFSET 0 > + > +#define MEMCLKMGR_EXTCNTRST_C0CNTRST BIT(7) > +#define MEMCLKMGR_EXTCNTRST_ALLCNTRST \ > + (MEMCLKMGR_EXTCNTRST_C0CNTRST) > + > +#endif /* _CLK_MEM_N5X_ */ > -- > 2.19.0 >
