On 26/05/21 10:35PM, Jagan Teki wrote: > On Mon, May 10, 2021 at 6:50 PM Pratyush Yadav <p.ya...@ti.com> wrote: > > > > Jagan, > > > > On 05/05/21 03:11PM, Pratyush Yadav wrote: > > > Hi, > > > > > > This series adds support for octal DTR flashes in the SPI NOR framework, > > > and then adds hooks for the Cypress S28HS512T and Micron MT35XU512ABA > > > flashes. > > > > > > The Cadence QSPI controller driver is also updated to run in Octal DTR > > > mode. > > > > > > Tested on TI J721E for MT35XU512ABA and J7200 for S28HS512T. Also tested > > > on M`T25QU512A for regressions. > > > > Can you please pick this series up as soon as possible? It makes lots of > > changes to the SPI NOR core. Let's cook this in next for a while to > > catch out any issues. This would avoid surprises close to the merge > > window. > > I have a plan to apply this to the next since it crosses the last MW. > can you send the footprint statistics? I can see and then apply next > on my repo to merge early MW.
On master (8ddaf94358): text data bss dec hex filename 950407 39608 56512 1046527 ff7ff u-boot With patches applied and Micron MT35 support enabled (for J721E): text data bss dec hex filename 953059 39632 56512 1049203 100273 u-boot Total difference: 2676 bytes. -- Regards, Pratyush Yadav Texas Instruments Inc.
