MAIN CPSW0 requires the PHY to be powered on and reset for QSGMII
operation. Add a env variable to configure driving "0" on ENET_EXP_PWRDN
controlled by GPIO EXPANDER2 (I2C Addr: 0x22), PIN: 17 and driving "1"
on ENET_EXP_RESETZ controlled by GPIO EXPANDER2 (I2C Addr: 0x22),
PIN: 18.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
Reviewed-by: Suman Anna <s-a...@ti.com>
---
include/configs/j721e_evm.h | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index b707fc4e89..00d0a18a68 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -139,11 +139,24 @@
#endif /* CONFIG_TARGET_J721E_A72_EVM */
#ifdef CONFIG_TARGET_J7200_A72_EVM
+#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \
+ "do_main_cpsw0_qsgmii_phyinit=1\0" \
+ "init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;" \
+ "gpio clear gpio@22_16\0" \
+ "main_cpsw0_qsgmii_phyinit=" \
+ "if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot}
-eq 1 && " \
+ "test ${boot} = mmc; then " \
+ "run init_main_cpsw0_qsgmii_phy;" \
+ "fi;\0"
#define DEFAULT_RPROCS "" \
"2 /lib/firmware/j7200-main-r5f0_0-fw " \
"3 /lib/firmware/j7200-main-r5f0_1-fw "
#endif /* CONFIG_TARGET_J7200_A72_EVM */
+#ifndef EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY
+#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY
+#endif
+
/* set default dfu_bufsiz to 128KB (sector size of OSPI) */
#define EXTRA_ENV_DFUARGS \
"dfu_bufsiz=0x20000\0" \
@@ -170,7 +183,8 @@
EXTRA_ENV_RPROC_SETTINGS \
EXTRA_ENV_DFUARGS \
DEFAULT_UFS_TI_ARGS \
- EXTRA_ENV_J721E_BOARD_SETTINGS_MTD
+ EXTRA_ENV_J721E_BOARD_SETTINGS_MTD \
+ EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>
--
2.17.1
