On Tue, Mar 2, 2021 at 11:18 PM Pali Rohár <p...@kernel.org> wrote: > > This syncs drivers/ddr/marvell/a38x/ with the master branch of repository > https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git up to the > commit 7c351731d196 ("Merge pull request #29 from pali/sync-a38x-uboot"). > > This patch was created by following steps: > > 1. Replace all a38x files in U-Boot tree by files from upstream github > Marvell mv-ddr-marvell repository. > > 2. Run following command to omit portions not relevant for a38x and ddr3: > > files=drivers/ddr/marvell/a38x/* > sed 's/#if defined(CONFIG_ARMADA_38X) || > defined(CONFIG_ARMADA_39X)/#ifdef TRUE/' -i $files > unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 -UCONFIG_APN806 \ > -UCONFIG_MC_STATIC -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \ > -UCONFIG_PHY_STATIC_PRINT -UCONFIG_CUSTOMER_BOARD_SUPPORT \ > -UCONFIG_A3700 -UA3900 -UA80X0 -UA70X0 -DTRUE $files > > 3. Manually omit SPDX-License-Identifier changes from this patch as > upstream license in upstream github repository contains long license > texts and U-Boot is using just SPDX-License-Identifier. > > After applying this patch, a38x ddr3 code in upstream Marvell github > repository and in U-Boot would be fully identical. So in future applying > above steps could be used to sync code again. > > The only change in this patch is removal of dead code and some fixes with > include files. > > Signed-off-by: Pali Rohár <p...@kernel.org> >
Taken for a spin on db-88f6820-amc and x530. Tested-by: Chris Packham <judge.pack...@gmail.com> > --- > > This patch depends on Marek's patch "ddr: marvell: a38x Add more space for > additional info from SPD" [1]. Please apply my patch on top Marek's patch. > > [1] - > https://patchwork.ozlabs.org/project/uboot/patch/20210226105659.3054-1-marek.be...@nic.cz/ > --- > drivers/ddr/marvell/a38x/ddr3_debug.c | 1 - > drivers/ddr/marvell/a38x/ddr3_init.c | 3 --- > drivers/ddr/marvell/a38x/ddr3_training.c | 11 +---------- > .../ddr/marvell/a38x/ddr3_training_ip_engine.c | 8 +++----- > drivers/ddr/marvell/a38x/ddr3_training_leveling.c | 1 - > drivers/ddr/marvell/a38x/ddr_ml_wrapper.h | 2 -- > drivers/ddr/marvell/a38x/mv_ddr_plat.c | 1 - > drivers/ddr/marvell/a38x/mv_ddr_plat.h | 2 ++ > drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.h | 15 --------------- > drivers/ddr/marvell/a38x/xor.c | 2 -- > 10 files changed, 6 insertions(+), 40 deletions(-) > > diff --git a/drivers/ddr/marvell/a38x/ddr3_debug.c > b/drivers/ddr/marvell/a38x/ddr3_debug.c > index 22e0cc4d9176..f5fc964d6f87 100644 > --- a/drivers/ddr/marvell/a38x/ddr3_debug.c > +++ b/drivers/ddr/marvell/a38x/ddr3_debug.c > @@ -6,7 +6,6 @@ > #include "ddr3_init.h" > #include "mv_ddr_training_db.h" > #include "mv_ddr_regs.h" > -#include <log.h> > > u8 is_reg_dump = 0; > u8 debug_pbs = DEBUG_LEVEL_ERROR; > diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c > b/drivers/ddr/marvell/a38x/ddr3_init.c > index 7488770268cf..f878b4512bfc 100644 > --- a/drivers/ddr/marvell/a38x/ddr3_init.c > +++ b/drivers/ddr/marvell/a38x/ddr3_init.c > @@ -77,9 +77,6 @@ int ddr3_init(void) > return status; > } > > -#if defined(CONFIG_PHY_STATIC_PRINT) > - mv_ddr_phy_static_print(); > -#endif > > /* Post MC/PHY initializations */ > mv_ddr_post_training_soc_config(ddr_type); > diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c > b/drivers/ddr/marvell/a38x/ddr3_training.c > index 2b3af23202b6..2512b58cb7b2 100644 > --- a/drivers/ddr/marvell/a38x/ddr3_training.c > +++ b/drivers/ddr/marvell/a38x/ddr3_training.c > @@ -7,8 +7,6 @@ > #include "mv_ddr_common.h" > #include "mv_ddr_training_db.h" > #include "mv_ddr_regs.h" > -#include <log.h> > -#include <linux/delay.h> > > #define GET_CS_FROM_MASK(mask) (cs_mask2_num[mask]) > #define CS_CBE_VALUE(cs_num) (cs_cbe_reg[cs_num]) > @@ -207,7 +205,6 @@ static int ddr3_tip_pad_inv(void) > if (tm->interface_params[0].as_bus_params[sphy]. > is_ck_swap == 1 && sphy == 0) { > /* TODO: move this code to per platform one */ > -#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) > /* clock swap for both cs0 and cs1 */ > data = (INVERT_PAD << INV_PAD2_OFFS | > INVERT_PAD << INV_PAD6_OFFS | > @@ -219,9 +216,6 @@ static int ddr3_tip_pad_inv(void) > DDR_PHY_CONTROL, > PHY_CTRL_PHY_REG, > data, data); > -#else /* !CONFIG_ARMADA_38X && !CONFIG_ARMADA_39X */ > -#pragma message "unknown platform to configure ddr clock swap" > -#endif > } > } > > @@ -2014,9 +2008,7 @@ int ddr3_tip_adll_regs_bypass(u32 dev_num, u32 > reg_val1, u32 reg_val2) > static int ddr3_tip_ddr3_training_main_flow(u32 dev_num) > { > /* TODO: enable this functionality for other platforms */ > -#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) > struct init_cntr_param init_cntr_prm; > -#endif > int ret = MV_OK; > int adll_bypass_flag = 0; > u32 if_id; > @@ -2050,7 +2042,6 @@ static int ddr3_tip_ddr3_training_main_flow(u32 dev_num) > } > > /* TODO: enable this functionality for other platforms */ > -#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) > if (is_adll_calib_before_init != 0) { > DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, > ("with adll calib before init\n")); > @@ -2081,7 +2072,6 @@ static int ddr3_tip_ddr3_training_main_flow(u32 dev_num) > return MV_FAIL; > } > } > -#endif > > ret = adll_calibration(dev_num, ACCESS_TYPE_MULTICAST, 0, freq); > if (ret != MV_OK) { > @@ -2905,3 +2895,4 @@ unsigned int mv_ddr_misl_phy_odt_n_get(void) > > return odt_n; > } > + > diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c > b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c > index 5fd9a052fa0d..102f9bd633f5 100644 > --- a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c > +++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c > @@ -6,8 +6,6 @@ > #include "ddr3_init.h" > #include "mv_ddr_regs.h" > #include "ddr_training_ip_db.h" > -#include <image.h> > -#include <linux/delay.h> > > #define PATTERN_1 0x55555555 > #define PATTERN_2 0xaaaaaaaa > @@ -614,9 +612,9 @@ int ddr3_tip_load_pattern_to_odpg(u32 dev_num, enum > hws_access_type access_type, > MASK_ALL_BITS)); > } > > - CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, > - ODPG_DATA_BUFFER_OFFS_REG, > - load_addr, MASK_ALL_BITS)); > + CHECK_STATUS(ddr3_tip_if_write > + (dev_num, access_type, if_id, > + ODPG_DATA_BUFFER_OFFS_REG, load_addr, MASK_ALL_BITS)); > > return MV_OK; > } > diff --git a/drivers/ddr/marvell/a38x/ddr3_training_leveling.c > b/drivers/ddr/marvell/a38x/ddr3_training_leveling.c > index dadb06b31814..7f7df6794a95 100644 > --- a/drivers/ddr/marvell/a38x/ddr3_training_leveling.c > +++ b/drivers/ddr/marvell/a38x/ddr3_training_leveling.c > @@ -7,7 +7,6 @@ > #include "mv_ddr_training_db.h" > #include "ddr_training_ip_db.h" > #include "mv_ddr_regs.h" > -#include <linux/delay.h> > > #define WL_ITERATION_NUM 10 > > diff --git a/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h > b/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h > index ac9250f74ed8..735731196589 100644 > --- a/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h > +++ b/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h > @@ -13,9 +13,7 @@ > #include <asm/arch/cpu.h> > #include <asm/arch/soc.h> > > -#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) > #define INTER_REGS_BASE SOC_REGS_PHY_BASE > -#endif > > /* > * MV_DEBUG_INIT need to be defines, otherwise the output of the > diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c > b/drivers/ddr/marvell/a38x/mv_ddr_plat.c > index 0d1df189e820..da0d63d4f7a4 100644 > --- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c > +++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c > @@ -8,7 +8,6 @@ > #include "mv_ddr_training_db.h" > #include "mv_ddr_regs.h" > #include "mv_ddr_sys_env_lib.h" > -#include <linux/delay.h> > > #define DDR_INTERFACES_NUM 1 > #define DDR_INTERFACE_OCTETS_NUM 5 > diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.h > b/drivers/ddr/marvell/a38x/mv_ddr_plat.h > index 281d4c23013e..44998847c254 100644 > --- a/drivers/ddr/marvell/a38x/mv_ddr_plat.h > +++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.h > @@ -6,6 +6,8 @@ > #ifndef _MV_DDR_PLAT_H > #define _MV_DDR_PLAT_H > > +#include <linux/delay.h> > + > #define MAX_DEVICE_NUM 1 > #define MAX_INTERFACE_NUM 1 > #define MAX_BUS_NUM 5 > diff --git a/drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.h > b/drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.h > index dc6977c33455..cf5142094d31 100644 > --- a/drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.h > +++ b/drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.h > @@ -78,20 +78,6 @@ enum suspend_wakeup_status { > * set '-2' > * If suspend to RAM is not supported set '-1' > */ > -#ifdef CONFIG_CUSTOMER_BOARD_SUPPORT > -#ifdef CONFIG_ARMADA_38X > -#define MV_BOARD_WAKEUP_GPIO_INFO { \ > - {A38X_CUSTOMER_BOARD_ID0, -1 }, \ > - {A38X_CUSTOMER_BOARD_ID0, -1 }, \ > -}; > -#else > -#define MV_BOARD_WAKEUP_GPIO_INFO { \ > - {A39X_CUSTOMER_BOARD_ID0, -1 }, \ > - {A39X_CUSTOMER_BOARD_ID0, -1 }, \ > -}; > -#endif /* CONFIG_ARMADA_38X */ > - > -#else > > #ifdef CONFIG_ARMADA_38X > #define MV_BOARD_WAKEUP_GPIO_INFO { \ > @@ -109,7 +95,6 @@ enum suspend_wakeup_status { > {A39X_DB_69XX_ID, -1 }, \ > }; > #endif /* CONFIG_ARMADA_38X */ > -#endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */ > > enum suspend_wakeup_status mv_ddr_sys_env_suspend_wakeup_check(void); > u32 mv_ddr_sys_env_get_cs_ena_from_reg(void); > diff --git a/drivers/ddr/marvell/a38x/xor.c b/drivers/ddr/marvell/a38x/xor.c > index 98fb39eaf0fa..7bc6268293e5 100644 > --- a/drivers/ddr/marvell/a38x/xor.c > +++ b/drivers/ddr/marvell/a38x/xor.c > @@ -347,10 +347,8 @@ void ddr3_new_tip_ecc_scrub(void) > for (cs_c = 0; cs_c < max_cs; cs_c++) > cs_ena |= 1 << cs_c; > > -#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) > /* all chip-selects are of same size */ > ddr3_calc_mem_cs_size(0, &cs_mem_size_mb); > -#endif > cs_mem_size = cs_mem_size_mb * _1M; > mv_sys_xor_init(max_cs, cs_ena, cs_mem_size, 0); > total_mem_size = max_cs * cs_mem_size; > -- > 2.20.1 >
