> -----Original Message-----
> From: Lim, Elly Siew Chin <elly.siew.chin....@intel.com>
> Sent: Saturday, February 27, 2021 12:58 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <ma...@denx.de>; Tan, Ley Foon
> <ley.foon....@intel.com>; See, Chin Liang <chin.liang....@intel.com>;
> Simon Goldschmidt <simon.k.r.goldschm...@gmail.com>; Chee, Tien Fong
> <tien.fong.c...@intel.com>; Westergreen, Dalon
> <dalon.westergr...@intel.com>; Simon Glass <s...@chromium.org>; Gan,
> Yau Wai <yau.wai....@intel.com>; Lim, Elly Siew Chin
> <elly.siew.chin....@intel.com>
> Subject: [RESEND v4 7/7] Makefile: socfpga: Add target to generate hex
> output for combined spl and dtb
>
> From: Dalon Westergreen <dalon.westergr...@intel.com>
>
> Add target to Makefile to generate "u-boot-spl-dtb.hex" for Intel SOCFPGA
> SOC64 devices (Stratix 10 and Agilex). "u-boot-spl-dtb.hex"
> is hex formatted spl with and offset of CONFIG_SPL_TEXT_BASE. It combines
> the spl image and dtb. "u-boot-spl-dtb.hex" is needed to generate the final
> configuration bitstream for Intel SOCFPGA SOC64 devices.
>
> Signed-off-by: Dalon Westergreen <dalon.westergr...@intel.com>
> Signed-off-by: Siew Chin Lim <elly.siew.chin....@intel.com>
>
> ---
> v4:
> - Replace CONFIG_TARGET_SOCFPGA_STRATIX10/AGILEX with
> CONFIG_TARGET_SOCFPGA_SOC64.
> - Add this patch into 'VAB' series because it is depending on
> CONFIG_TARGET_SOCFPGA_SOC64 patch.
> ---
> Makefile | 11 ++++++-----
> include/configs/socfpga_soc64_common.h | 2 +-
> scripts/Makefile.spl | 7 +++++++
> 3 files changed, 14 insertions(+), 6 deletions(-)
Reviewed-by: Ley Foon Tan <ley.foon....@intel.com>
Regards
Ley Foon
