On 22/02/2021 22:11, Bob wrote: Hi Bob,
> Lower DRAM clock speed to the official speed for the pinephone design: 528 Can you elaborate why this is necessary? Are there reports with the existing data rate causing problems? Please keep in mind that the whole DRAM timings we use do not confirm to any JEDEC standards, mostly the parameters are derived from some Allwinner provided data. Since the clock frequency is connected to the timing parameters (many values are defined in terms of number of cycles), just lowering the frequency can have any kind of effects. > Signed-off-by: Bobby The Builder <b...@najdan.com> Since this is a legal statement, I am afraid it has to carry your real name. Cheers, Andre > --- > configs/pinephone_defconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/configs/pinephone_defconfig b/configs/pinephone_defconfig > index d8ee930a69..702e2bdc14 100644 > --- a/configs/pinephone_defconfig > +++ b/configs/pinephone_defconfig > @@ -4,7 +4,7 @@ CONFIG_SPL=y > CONFIG_PINEPHONE_LEDS=y > CONFIG_MACH_SUN50I=y > CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y > -CONFIG_DRAM_CLK=552 > +CONFIG_DRAM_CLK=528 > CONFIG_DRAM_ZQ=3881949 > CONFIG_MMC_SUNXI_SLOT_EXTRA=2 > CONFIG_PINEPHONE_DT_SELECTION=y
