DTS files apart from r8a774b1-hihope-rzg2n-u-boot.dts and
r8a774b1-u-boot.dtsi have been imported from linux 5.10
commit 2c85ebc57b3e1817b6c ("Linux 5.10").

Signed-off-by: Biju Das <biju.das...@bp.renesas.com>
---
 arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts     | 21 ++++++++
 arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts | 27 ++++++++++
 arch/arm/dts/r8a774b1-hihope-rzg2n.dts        | 41 ++++++++++++++
 arch/arm/dts/r8a774b1-u-boot.dtsi             | 53 +++++++++++++++++++
 4 files changed, 142 insertions(+)
 create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
 create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
 create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n.dts
 create mode 100644 arch/arm/dts/r8a774b1-u-boot.dtsi

diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts 
b/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
new file mode 100644
index 0000000000..58812b41ac
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2N Rev.3.0/4.0 connected to
+ * sub board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include "r8a774b1-hihope-rzg2n.dts"
+#include "hihope-rzg2-ex.dtsi"
+
+/ {
+       model = "HopeRun HiHope RZ/G2N with sub board";
+       compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2n",
+                    "renesas,r8a774b1";
+};
+
+/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */
+&sata {
+       status = "okay";
+};
diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts 
b/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
new file mode 100644
index 0000000000..0bdc6909bf
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Hihope RZ/G2N board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include "r8a774b1-hihope-rzg2n-ex.dts"
+#include "r8a774b1-u-boot.dtsi"
+
+&gpio3 {
+       bt_reg_on{
+               gpio-hog;
+               gpios = <13 GPIO_ACTIVE_HIGH>;
+               output-low;
+               line-name = "bt-reg-on";
+       };
+};
+
+&gpio4 {
+       wlan_reg_on{
+               gpio-hog;
+               gpios = <6 GPIO_ACTIVE_HIGH>;
+               output-low;
+               line-name = "wlan-reg-on";
+       };
+};
diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n.dts 
b/arch/arm/dts/r8a774b1-hihope-rzg2n.dts
new file mode 100644
index 0000000000..b90790a95b
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-hihope-rzg2n.dts
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2N main board Rev.3.0/4.0
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a774b1.dtsi"
+#include "hihope-rev4.dtsi"
+
+/ {
+       model = "HopeRun HiHope RZ/G2N main board based on r8a774b1";
+       compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1";
+
+       memory@48000000 {
+               device_type = "memory";
+               /* first 128MB is reserved for secure area. */
+               reg = <0x0 0x48000000 0x0 0x78000000>;
+       };
+
+       memory@480000000 {
+               device_type = "memory";
+               reg = <0x4 0x80000000 0x0 0x80000000>;
+       };
+};
+
+&du {
+       clocks = <&cpg CPG_MOD 724>,
+                <&cpg CPG_MOD 723>,
+                <&cpg CPG_MOD 721>,
+                <&versaclock5 1>,
+                <&x302_clk>,
+                <&versaclock5 2>;
+       clock-names = "du.0", "du.1", "du.3",
+                     "dclkin.0", "dclkin.1", "dclkin.3";
+};
+
+&sdhi3 {
+       mmc-hs400-1_8v;
+};
diff --git a/arch/arm/dts/r8a774b1-u-boot.dtsi 
b/arch/arm/dts/r8a774b1-u-boot.dtsi
new file mode 100644
index 0000000000..6fab78e776
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-u-boot.dtsi
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot on RZ/G2 R8A774B1 SoC
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+&extalr_clk {
+       u-boot,dm-pre-reloc;
+};
+
+/delete-node/ &audma0;
+/delete-node/ &audma1;
+/delete-node/ &can0;
+/delete-node/ &can1;
+/delete-node/ &canfd;
+/delete-node/ &csi20;
+/delete-node/ &csi40;
+/delete-node/ &du;
+/delete-node/ &fcpf0;
+/delete-node/ &fcpvb0;
+/delete-node/ &fcpvd0;
+/delete-node/ &fcpvd1;
+/delete-node/ &fcpvi0;
+/delete-node/ &hdmi0;
+/delete-node/ &lvds0;
+/delete-node/ &rcar_sound;
+/delete-node/ &sdhi2;
+/delete-node/ &sound_card;
+/delete-node/ &vin0;
+/delete-node/ &vin1;
+/delete-node/ &vin2;
+/delete-node/ &vin3;
+/delete-node/ &vin4;
+/delete-node/ &vin5;
+/delete-node/ &vin6;
+/delete-node/ &vin7;
+/delete-node/ &vspb;
+/delete-node/ &vspd0;
+/delete-node/ &vspd1;
+/delete-node/ &vspi0;
+
+/ {
+       /delete-node/ hdmi0-out;
+};
+
+/ {
+       soc {
+               /delete-node/ fdp1@fe940000;
+       };
+};
-- 
2.17.1

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