Hi All,
There is a typo in comments in original commit message. The correct values are
as follows.
with v8:
--------
$ size spl/arch/arm/mach-rmobile/cpu_info.o
text data bss dec hex filename
330 0 0 330 14a
spl/arch/arm/mach-rmobile/cpu_info.o
$ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
-rw-r--r-- 1 biju biju 9176 Jan 16 18:10
spl/arch/arm/mach-rmobile/cpu_info.o
$ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o
-rw-r--r-- 1 biju biju 6244 Jan 16 18:30
spl/arch/arm/mach-rmobile/cpu_info-rcar.o
$ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o
text data bss dec hex filename
120 0 0 120 78
spl/arch/arm/mach-rmobile/cpu_info-rcar.o
with v7:
--------
$ size spl/arch/arm/mach-rmobile/cpu_info.o
text data bss dec hex filename
462 0 0 462 1ce
spl/arch/arm/mach-rmobile/cpu_info.o
$ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
-rw-r--r-- 1 biju biju 9308 Jan 16 17:28
spl/arch/arm/mach-rmobile/cpu_info.o
$ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o
-rw-r--r-- 1 biju biju 6864 Jan 16 18:28
spl/arch/arm/mach-rmobile/cpu_info-rcar.o
$ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o
text data bss dec hex filename
154 0 0 154 9a
spl/arch/arm/mach-rmobile/cpu_info-rcar.o
Regards,
Biju
> Subject: [PATCH v8 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support
>
> RZ/G2 SoC's are identical to R-Car Gen3 SoC's apart from some automotive
> peripherals.
>
> RZ/G2H (R8A774E1) = R-Car H3-N (R8A77951).
> RZ/G2M (R8A774A1) = R-Car M3-W (R8A77960).
> RZ/G2N (R8A774B1) = R-Car M3-N (R8A77965).
> RZ/G2E (R8A774C0) = R-Car E3 (R8A77990).
>
> As the devices are the same they also have the same SoC PRR register
> values. SoC driver is used to distinguish the cpu type based on the
> family.
>
> Signed-off-by: Biju Das <biju.das...@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com>
> ---
> v7->v8
> * Optimized the cpu detection image size, when Renesas SoC identification
> driver is disabled for R-Car Gen2 SPL builds
>
> with v8:
> --------
> $ size spl/arch/arm/mach-rmobile/cpu_info.o
> text data bss dec hex filename
> 462 0 0 462 1ce
> spl/arch/arm/mach-rmobile/cpu_info.o
>
> $ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
> -rw-r--r-- 1 biju biju 9308 Jan 16 17:28 spl/arch/arm/mach-
> rmobile/cpu_info.o
>
> $ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o
> -rw-r--r-- 1 biju biju 6864 Jan 16 18:28 spl/arch/arm/mach-
> rmobile/cpu_info-rcar.o
>
> $ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o
> text data bss dec hex filename
> 154 0 0 154 9a
> spl/arch/arm/mach-rmobile/cpu_info-rcar.o
>
> with v7:
> --------
> $ size spl/arch/arm/mach-rmobile/cpu_info.o
> text data bss dec hex filename
> 330 0 0 330 14a
> spl/arch/arm/mach-rmobile/cpu_info.o
>
> $ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
> -rw-r--r-- 1 biju biju 9176 Jan 16 18:10 spl/arch/arm/mach-
> rmobile/cpu_info.o
>
> $ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o
> -rw-r--r-- 1 biju biju 6244 Jan 16 18:30 spl/arch/arm/mach-
> rmobile/cpu_info-rcar.o
>
> $ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o
> text data bss dec hex filename
> 120 0 0 120 78
> spl/arch/arm/mach-rmobile/cpu_info-rcar.o
>
> v6->v7
> * Seperated driver patch series from board support patches.
> v5->v6
> * Optimized the unique CPU identification method by using Renesas SoC
> identification driver.
> v4->v5
> * Add support for unique identification of RZ/G2 CPU types
> (Ref:
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.ozlabs.org%2Fproject%2Fuboot%2Fpatch%2F20201008085941.3600-1-
> biju.das.jz%40bp.renesas.com%2F&data=04%7C01%7Cbiju.das.jz%40bp.renesa
> s.com%7Cf359d4ea30294c1866b008d8ba5e79d4%7C53d82571da1947e49cb4625a166a4a2
> a%7C0%7C0%7C637464262268730689%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDA
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=s2xAHTFxU
> JuB%2FQwRRMVoQ37EDOgqvZqceenB6v3RFp8%3D&reserved=0)
> v3->v4
> * Dropped CPU info reporting logic for RZ/G2. Will address this later.
> * Added PRRID's for RZG2[HMNE]
> (Ref:
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.ozlabs.org%2Fproject%2Fuboot%2Fpatch%2F20201001103658.4835-1-
> biju.das.jz%40bp.renesas.com%2F&data=04%7C01%7Cbiju.das.jz%40bp.renesa
> s.com%7Cf359d4ea30294c1866b008d8ba5e79d4%7C53d82571da1947e49cb4625a166a4a2
> a%7C0%7C0%7C637464262268730689%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDA
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=v3ecivGm4
> %2B%2FuqKlGv20Cf9iJh%2Br41NeCpm4wFoKFuHY%3D&reserved=0)
>
> v2->v3
> * Reworked as per Marek's suggestion
> * Added rzg2_get_cpu_type function to get cpu_type by matching TFA
> compatible string
> * Removed SoC family type Enum
> (Ref:
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.ozlabs.org%2Fproject%2Fuboot%2Fpatch%2F20200922160317.16296-2-
> biju.das.jz%40bp.renesas.com%2F&data=04%7C01%7Cbiju.das.jz%40bp.renesa
> s.com%7Cf359d4ea30294c1866b008d8ba5e79d4%7C53d82571da1947e49cb4625a166a4a2
> a%7C0%7C0%7C637464262268730689%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDA
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=HGQE08DH0
> uRGy1C%2Fi1mZUUWHm%2FzAAR%2Bl995O8H1SGsc%3D&reserved=0)
>
> v1->v2:
> * Add comment's related to loop logic
> (ref:
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.ozlabs.org%2Fproject%2Fuboot%2Fpatch%2F20200918160307.14323-1-
> biju.das.jz%40bp.renesas.com%2F&data=04%7C01%7Cbiju.das.jz%40bp.renesa
> s.com%7Cf359d4ea30294c1866b008d8ba5e79d4%7C53d82571da1947e49cb4625a166a4a2
> a%7C0%7C0%7C637464262268730689%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDA
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=VnyOQwVJj
> cf1MCA8ylvf4vfZ%2Bo%2Bv52q2o%2FCfKKuDtZM%3D&reserved=0)
>
> v1:
> * New patch
>
> (ref:https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat
> chwork.ozlabs.org%2Fproject%2Fuboot%2Fpatch%2F20200915143630.7678-4-
> biju.das.jz%40bp.renesas.com%2F&data=04%7C01%7Cbiju.das.jz%40bp.renesa
> s.com%7Cf359d4ea30294c1866b008d8ba5e79d4%7C53d82571da1947e49cb4625a166a4a2
> a%7C0%7C0%7C637464262268730689%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDA
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=nFnGgVT%2
> FSNZEqiwCDjnmvUqQEy7LOjiQDac3JMCAyBc%3D&reserved=0
> ---
> arch/arm/mach-rmobile/Makefile | 7 +++
> arch/arm/mach-rmobile/cpu_info-rcar.c | 20 ++++++-
> arch/arm/mach-rmobile/cpu_info.c | 12 +++-
> arch/arm/mach-rmobile/include/mach/rmobile.h | 63 +++++++++++++++-----
> arch/arm/mach-rmobile/soc_family-info.c | 21 +++++++
> 5 files changed, 102 insertions(+), 21 deletions(-) create mode 100644
> arch/arm/mach-rmobile/soc_family-info.c
>
> diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-
> rmobile/Makefile index 3206bce722..305dee87e2 100644
> --- a/arch/arm/mach-rmobile/Makefile
> +++ b/arch/arm/mach-rmobile/Makefile
> @@ -13,6 +13,13 @@ obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-
> sh73a0.o pfc-sh73a0.o
> obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
> obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
> obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-
> gen3.o
> +obj-$(CONFIG_RCAR_GEN3) += soc_family-info.o
> +
> +ifeq ($(CONFIG_RCAR_GEN2),y)
> +ifneq ($(CONFIG_SPL_BUILD),y)
> +obj-y += soc_family-info.o
> +endif
> +endif
>
> OBJCOPYFLAGS_u-boot-spl.srec := -O srec quiet_cmd_objcopy = OBJCOPY $@
> diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c b/arch/arm/mach-
> rmobile/cpu_info-rcar.c
> index 5bde24ae0e..7d162235d2 100644
> --- a/arch/arm/mach-rmobile/cpu_info-rcar.c
> +++ b/arch/arm/mach-rmobile/cpu_info-rcar.c
> @@ -1,8 +1,8 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> - * arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c
> + * arch/arm/mach-rmobile/cpu_info-rcar.c
> *
> - * Copyright (C) 2013,2014 Renesas Electronics Corporation
> + * Copyright (C) 2013-2021 Renesas Electronics Corporation
> */
> #include <common.h>
> #include <asm/io.h>
> @@ -12,6 +12,15 @@
> #define R8A7796_REV_1_1 0x5210
> #define R8A7796_REV_1_3 0x5211
>
> +#if defined(CONFIG_RCAR_GEN2) && defined(CONFIG_SPL_BUILD) static bool
> +__is_rzg_family(void) {
> + return false;
> +}
> +bool is_rzg_family(void)
> + __attribute__((weak, alias("__is_rzg_family"))); #endif
> +
> static u32 rmobile_get_prr(void)
> {
> #ifdef CONFIG_RCAR_GEN3
> @@ -23,7 +32,12 @@ static u32 rmobile_get_prr(void)
>
> u32 rmobile_get_cpu_type(void)
> {
> - return (rmobile_get_prr() & 0x00007F00) >> 8;
> + u32 soc_id = (rmobile_get_prr() & 0x7F00) >> 8;
> +
> + if (is_rzg_family())
> + soc_id |= RZG_CPU_MASK;
> +
> + return soc_id;
> }
>
> u32 rmobile_get_cpu_rev_integer(void)
> diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-
> rmobile/cpu_info.c
> index fdbbd72e28..2555fa4903 100644
> --- a/arch/arm/mach-rmobile/cpu_info.c
> +++ b/arch/arm/mach-rmobile/cpu_info.c
> @@ -3,12 +3,12 @@
> * (C) Copyright 2012 Nobuhiro Iwamatsu
> <nobuhiro.iwamatsu...@renesas.com>
> * (C) Copyright 2012 Renesas Solutions Corp.
> */
> -#include <common.h>
> -#include <cpu_func.h>
> #include <asm/cache.h>
> -#include <init.h>
> #include <asm/io.h>
> +#include <common.h>
> +#include <cpu_func.h>
> #include <env.h>
> +#include <init.h>
> #include <linux/ctype.h>
>
> #ifdef CONFIG_ARCH_CPU_INIT
> @@ -64,6 +64,11 @@ static const struct {
> { RMOBILE_CPU_TYPE_R8A7792, "R8A7792" },
> { RMOBILE_CPU_TYPE_R8A7793, "R8A7793" },
> { RMOBILE_CPU_TYPE_R8A7794, "R8A7794" },
> +#ifdef CONFIG_RCAR_GEN3
> + { RMOBILE_CPU_TYPE_R8A774A1, "R8A774A1" },
> + { RMOBILE_CPU_TYPE_R8A774B1, "R8A774B1" },
> + { RMOBILE_CPU_TYPE_R8A774C0, "R8A774C0" },
> + { RMOBILE_CPU_TYPE_R8A774E1, "R8A774E1" },
> { RMOBILE_CPU_TYPE_R8A7795, "R8A7795" },
> { RMOBILE_CPU_TYPE_R8A7796, "R8A7796" },
> { RMOBILE_CPU_TYPE_R8A77965, "R8A77965" }, @@ -71,6 +76,7 @@ static
> const struct {
> { RMOBILE_CPU_TYPE_R8A77980, "R8A77980" },
> { RMOBILE_CPU_TYPE_R8A77990, "R8A77990" },
> { RMOBILE_CPU_TYPE_R8A77995, "R8A77995" },
> +#endif
> { 0x0, "CPU" },
> };
>
> diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-
> rmobile/include/mach/rmobile.h
> index a50249dc96..58e51e8df2 100644
> --- a/arch/arm/mach-rmobile/include/mach/rmobile.h
> +++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
> @@ -1,6 +1,8 @@
> #ifndef __ASM_ARCH_RMOBILE_H
> #define __ASM_ARCH_RMOBILE_H
>
> +#include <stdbool.h>
> +
> #if defined(CONFIG_ARCH_RMOBILE)
> #if defined(CONFIG_SH73A0)
> #include <asm/arch/sh73a0.h>
> @@ -24,23 +26,54 @@
> #endif
> #endif /* CONFIG_ARCH_RMOBILE */
>
> -/* PRR CPU IDs */
> -#define RMOBILE_CPU_TYPE_SH73A0 0x37
> -#define RMOBILE_CPU_TYPE_R8A7740 0x40
> -#define RMOBILE_CPU_TYPE_R8A7790 0x45
> -#define RMOBILE_CPU_TYPE_R8A7791 0x47
> -#define RMOBILE_CPU_TYPE_R8A7792 0x4A
> -#define RMOBILE_CPU_TYPE_R8A7793 0x4B
> -#define RMOBILE_CPU_TYPE_R8A7794 0x4C
> -#define RMOBILE_CPU_TYPE_R8A7795 0x4F
> -#define RMOBILE_CPU_TYPE_R8A7796 0x52
> -#define RMOBILE_CPU_TYPE_R8A77965 0x55
> -#define RMOBILE_CPU_TYPE_R8A77970 0x54
> -#define RMOBILE_CPU_TYPE_R8A77980 0x56
> -#define RMOBILE_CPU_TYPE_R8A77990 0x57
> -#define RMOBILE_CPU_TYPE_R8A77995 0x58
> +/* PRR IDs */
> +#define SOC_ID_SH73A0 0x37
> +#define SOC_ID_R8A7740 0x40
> +#define SOC_ID_R8A774A1 0x52
> +#define SOC_ID_R8A774B1 0x55
> +#define SOC_ID_R8A774C0 0x57
> +#define SOC_ID_R8A774E1 0x4F
> +#define SOC_ID_R8A7790 0x45
> +#define SOC_ID_R8A7791 0x47
> +#define SOC_ID_R8A7792 0x4A
> +#define SOC_ID_R8A7793 0x4B
> +#define SOC_ID_R8A7794 0x4C
> +#define SOC_ID_R8A7795 0x4F
> +#define SOC_ID_R8A7796 0x52
> +#define SOC_ID_R8A77965 0x55
> +#define SOC_ID_R8A77970 0x54
> +#define SOC_ID_R8A77980 0x56
> +#define SOC_ID_R8A77990 0x57
> +#define SOC_ID_R8A77995 0x58
> +
> +/* CPU IDs */
> +#define RMOBILE_CPU_TYPE_SH73A0 SOC_ID_SH73A0
> +#define RMOBILE_CPU_TYPE_R8A7740 SOC_ID_R8A7740
> +#define RMOBILE_CPU_TYPE_R8A774A1 (SOC_ID_R8A774A1 | RZG_CPU_MASK)
> +#define RMOBILE_CPU_TYPE_R8A774B1 (SOC_ID_R8A774B1 | RZG_CPU_MASK)
> +#define RMOBILE_CPU_TYPE_R8A774C0 (SOC_ID_R8A774C0 | RZG_CPU_MASK)
> +#define RMOBILE_CPU_TYPE_R8A774E1 (SOC_ID_R8A774E1 | RZG_CPU_MASK)
> +#define RMOBILE_CPU_TYPE_R8A7790 SOC_ID_R8A7790
> +#define RMOBILE_CPU_TYPE_R8A7791 SOC_ID_R8A7791
> +#define RMOBILE_CPU_TYPE_R8A7792 SOC_ID_R8A7792
> +#define RMOBILE_CPU_TYPE_R8A7793 SOC_ID_R8A7793
> +#define RMOBILE_CPU_TYPE_R8A7794 SOC_ID_R8A7794
> +#define RMOBILE_CPU_TYPE_R8A7795 SOC_ID_R8A7795
> +#define RMOBILE_CPU_TYPE_R8A7796 SOC_ID_R8A7796
> +#define RMOBILE_CPU_TYPE_R8A77965 SOC_ID_R8A77965
> +#define RMOBILE_CPU_TYPE_R8A77970 SOC_ID_R8A77970
> +#define RMOBILE_CPU_TYPE_R8A77980 SOC_ID_R8A77980
> +#define RMOBILE_CPU_TYPE_R8A77990 SOC_ID_R8A77990
> +#define RMOBILE_CPU_TYPE_R8A77995 SOC_ID_R8A77995
> +
> +/*
> + * R-Car and RZ/G SoC's share same PRR ID's for the same SoC type. The
> + * RZG_CPU_MASK is used to provide a unique CPU identification for RZ/G
> SoC's.
> + */
> +#define RZG_CPU_MASK 0x1000
>
> #ifndef __ASSEMBLY__
> +bool is_rzg_family(void);
> u32 rmobile_get_cpu_type(void);
> u32 rmobile_get_cpu_rev_integer(void);
> u32 rmobile_get_cpu_rev_fraction(void);
> diff --git a/arch/arm/mach-rmobile/soc_family-info.c b/arch/arm/mach-
> rmobile/soc_family-info.c
> new file mode 100644
> index 0000000000..f09bd1a79f
> --- /dev/null
> +++ b/arch/arm/mach-rmobile/soc_family-info.c
> @@ -0,0 +1,21 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2021 Renesas Electronics Corporation
> + *
> + */
> +#include <common.h>
> +#include <soc.h>
> +
> +bool is_rzg_family(void)
> +{
> + bool rzg_family_type = false;
> + struct udevice *soc;
> + char name[16];
> +
> + if (!(soc_get(&soc) || soc_get_family(soc, name, 16))) {
> + if (!strcmp(name, "RZ/G2"))
> + rzg_family_type = true;
> + }
> +
> + return rzg_family_type;
> +}
> --
> 2.17.1
