Hi Jaehoon
I had already mentioned about making more readable than now.
>
> if (rate <= 1000000) {
> rdelay = wdelay = OWL_SD_DELAY_LOW_CLK;
> } else if ( ...) {
> rdelay = wdelay = OWL_SD_DELAY_MID_CLK;
> } else if (....) {
> rdelay = OWL_SD_RDELAY_HIGH;
> wdelay = OWL_SD_WDELAY_HIGH;
> }
>
> writel(reg | OWL_SD_CTRL_RDELAY(rdelay) | OWL_SD_CTL_WDELAY(wdelay)...);
>
> There are many approach to make readable..but Amit mentioned it's using
> same code in Linux kernel driver.
>
> To be honest, this is *not* the reason but if you see controller also
> supports DDR50 mode(which we may support in future)
where we have different values for read and write delays and we may need
that many variables to write it cleanly.
But if this is not the problem , I will implement the changes as
suggested by you.
>
> > Thanks
> > -Amit
> >
>
>
