Hi Marek,
From: Marek Vasut <ma...@denx.de>
Sent: mardi 1 décembre 2020 11:35
The LAN8710i PHY currently uses 50 MHz clock direct from PLL4P.
To permit PLL4P to run at faster frequency, use MCO2 as a divider.
The PLL4P runs at 100 MHz, supplies MCO2 which divides it by 2 to 50MHz, and
supplies the PHY with 50 MHz via pin PG2. The feedback clock are fed back in
via pin PA1.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Patrice Chotard <patrice.chot...@st.com>
Cc: Patrick Delaunay <patrick.delau...@st.com>
---
NOTE: This is for next
---
arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 25 +++++++++++++++++-----
arch/arm/dts/stm32mp15xx-dhcom.dtsi | 3 +--
2 files changed, 21 insertions(+), 7 deletions(-)
Reviewed-by: Patrick Delaunay <patrick.delau...@foss.st.com>
Thanks Patrick
