> -----Original Message-----
> From: Lim, Elly Siew Chin <elly.siew.chin....@intel.com>
> Sent: Tuesday, November 10, 2020 2:45 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <ma...@denx.de>; Tan, Ley Foon
> <ley.foon....@intel.com>; See, Chin Liang <chin.liang....@intel.com>;
> Simon Goldschmidt <simon.k.r.goldschm...@gmail.com>; Chee, Tien Fong
> <tien.fong.c...@intel.com>; Westergreen, Dalon
> <dalon.westergr...@intel.com>; Simon Glass <s...@chromium.org>; Gan,
> Yau Wai <yau.wai....@intel.com>; Lim, Elly Siew Chin
> <elly.siew.chin....@intel.com>
> Subject: [RESEND v2 20/22] arm: dts: dm: Add base dtsi and devkit dts for
> Diamond Mesa
>
> Add device tree for Diamond Mesa.
>
> Signed-off-by: Siew Chin Lim <elly.siew.chin....@intel.com>
> Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com>
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/socfpga_dm-u-boot.dtsi | 102 +++++
> arch/arm/dts/socfpga_dm.dtsi | 640
> ++++++++++++++++++++++++++++++
> arch/arm/dts/socfpga_dm_socdk-u-boot.dtsi | 50 +++
> arch/arm/dts/socfpga_dm_socdk.dts | 144 +++++++
> 5 files changed, 937 insertions(+)
> create mode 100644 arch/arm/dts/socfpga_dm-u-boot.dtsi
> create mode 100644 arch/arm/dts/socfpga_dm.dtsi create mode 100644
> arch/arm/dts/socfpga_dm_socdk-u-boot.dtsi
> create mode 100644 arch/arm/dts/socfpga_dm_socdk.dts
>
> diff --git a/arch/arm/dts/socfpga_dm.dtsi b/arch/arm/dts/socfpga_dm.dtsi
Make sure sync latest from Linux.
[...]
> + };
> + gmac0: ethernet@ff800000 {
Add new line before gmac0.
[...]
> diff --git a/arch/arm/dts/socfpga_dm_socdk-u-boot.dtsi
> b/arch/arm/dts/socfpga_dm_socdk-u-boot.dtsi
> new file mode 100644
> index 0000000000..9dbcaf2eb0
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_dm_socdk-u-boot.dtsi
> @@ -0,0 +1,50 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * U-Boot additions
> + *
> + * Copyright (C) 2020 Intel Corporation <www.intel.com> */
> +
> +#include "socfpga_dm-u-boot.dtsi"
> +
> +/{
> + aliases {
> + spi0 = &qspi;
> + i2c0 = &i2c1;
> + };
> +
> + memory {
> + /* 8GB */
> + reg = <0 0x00000000 0 0x80000000>,
> + <2 0x80000000 1 0x80000000>;
> + };
> +};
> +
> +&flash0 {
> + compatible = "jedec,spi-nor";
> + spi-tx-bus-width = <4>;
> + spi-rx-bus-width = <4>;
> + u-boot,dm-pre-reloc;
> +};
> +
> +&i2c1 {
> + status = "okay";
> +};
> +
> +&nand {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&mmc {
> + drvsel = <3>;
> + smplsel = <0>;
> + u-boot,dm-pre-reloc;
> +};
> +
> +&qspi {
> + status = "okay";
> +};
socfpga_dm_socdk.dts already set this.
Regards
Ley Foon
