replace PTR_LA in the very begining, e.g. in
arch/mips/cpu/start.S
arch/mips/lib/cache_init.S
to write position independence code. this is helpfull for make
single binary can be loaded to different ram/rom addresses.
FIXME: only tested on 32 bit system
Signed-off-by: Du Huanpeng <d...@hodcarrier.cn>
---
arch/mips/include/asm/asm.h | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
index a6876e1..f93281f 100644
--- a/arch/mips/include/asm/asm.h
+++ b/arch/mips/include/asm/asm.h
@@ -289,6 +289,27 @@ symbol = value
#define PTRLOG 3
#endif
+#ifdef __ASSEMBLER__
+/*
+ * helpers for writing position independence code
+ * FIXME: only tested on 32 bit system
+ */
+ .macro REL_LA reg lable
+ .set push
+ .set noat
+ .set noreorder
+ move $at, $ra /* preserve ra */
+ bal 888f
+ nop
+888: la \reg, 888b
+ subu \reg, $ra, \reg /* offset store in reg */
+ move $ra, $at /* restroe ra */
+ la $at, \lable
+ addu \reg, $at, \reg
+ .set pop
+ .endm
+#endif
+
/*
* Some cp0 registers were extended to 64bit for MIPS III.
*/
--
2.7.4
