At present this is defined in the header file, along with a few related defines. The code that used to need this has been removed. Move it into the C file instead.
Signed-off-by: Simon Glass <s...@chromium.org> --- arch/x86/include/asm/tables.h | 8 -------- arch/x86/lib/tables.c | 8 ++++++++ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/tables.h b/arch/x86/include/asm/tables.h index bf66e79018e..ff15949bd47 100644 --- a/arch/x86/include/asm/tables.h +++ b/arch/x86/include/asm/tables.h @@ -8,14 +8,6 @@ #include <tables_csum.h> -#define ROM_TABLE_ADDR CONFIG_ROM_TABLE_ADDR -#define ROM_TABLE_END (CONFIG_ROM_TABLE_ADDR + CONFIG_ROM_TABLE_SIZE - 1) - -#define ROM_TABLE_ALIGN 1024 - -/* SeaBIOS expects coreboot tables at address range 0x0000-0x1000 */ -#define CB_TABLE_ADDR 0x800 - /** * table_compute_checksum() - Compute a table checksum * diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index 7099866a78a..43b61a7aeac 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -13,6 +13,14 @@ #include <asm/tables.h> #include <asm/coreboot_tables.h> +#define ROM_TABLE_ADDR CONFIG_ROM_TABLE_ADDR +#define ROM_TABLE_END (CONFIG_ROM_TABLE_ADDR + CONFIG_ROM_TABLE_SIZE - 1) + +#define ROM_TABLE_ALIGN 1024 + +/* SeaBIOS expects coreboot tables at address range 0x0000-0x1000 */ +#define CB_TABLE_ADDR 0x800 + /** * Function prototype to write a specific configuration table * -- 2.28.0.681.g6f77f65b4e-goog
