On Wed, 8 Sep 2010 23:36:59 +0200
Ilya Yanok <ya...@emcraft.com> wrote:
>
> MAINTAINERS | 1 +
> board/mpc8308_p1m/Makefile | 52 ++++
> board/mpc8308_p1m/config.mk | 1 +
> board/mpc8308_p1m/mpc8308_p1m.c | 122 +++++++++
> board/mpc8308_p1m/sdram.c | 93 +++++++
> boards.cfg | 1 +
> include/configs/mpc8308_p1m.h | 548
> +++++++++++++++++++++++++++++++++++++++
missing MAKEALL entry.
> +++ b/board/mpc8308_p1m/config.mk
> @@ -0,0 +1 @@
> +TEXT_BASE = 0xFC000000
ifndef TEXT_BASE
TEXT_BASE = 0xFC000000
endif
> +int board_early_init_f(void)
> +{
> + immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
> +
> + if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF)
> + gd->flags |= GD_FLG_SILENT;
this needs to be deleted - the 8308 doesn't have a pmccr1. Same
problem with the 8308rdb.
> + /* initialized GPIO default directions and values */
> + __raw_writel(CONFIG_GPIO_PDAT, &im->gpio[0].dat);
> + __raw_writel(CONFIG_GPIO_PDIR, &im->gpio[0].dir);
> +
is there a reason CONFIG_SYS_GPIO1_[DIR|DAT] isn't being used instead
of declaring new CONFIG_GPIO_P* macros?
> +void pci_init_board(void)
> + clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM ,
> + SCCR_PCIEXP1CM_1);
add support for setting sccr PCIEXPCM bits in mpc83xx/cpu_init.c, and
define CONFIG_SYS_SCCR_ values in the board config.
> +int board_eth_init(bd_t *bis)
> +{
> + int rv, num_if = 0;
> +
> + /* Initialize TSECs first */
> + if ((rv = cpu_eth_init(bis)) >= 0)
no assignments in if statements.
> + * System IO Config
> + */
> +#define CONFIG_SYS_SICRH 0xf577d100
> +#define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */
Use the SICR[H|L]_ macros to demystify these values (same for 8308erdb).
> +/* GPIO Default input/output settings */
> +#define CONFIG_GPIO_PDIR 0x7AAF8C00
this should be defining CONFIG_SYS_GPIO1_DIR instead.
> +/*
> + * Default GPIO values:
> + * LED#1 enabled; WLAN enabled; Both COM LED on (orange)
> + */
> +#define CONFIG_GPIO_PDAT 0x08008C00
this should be defining CONFIG_SYS_GPIO1_DAT instead.
> +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_SJA1000_BASE
> +#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
lose the comment and replace with (LBLAWAR_EN | LBLAWAR_32KB).
> +/*
> + * CPLD on Local Bus
> + */
> +#define CONFIG_SYS_CPLD_BASE 0xFBFF8000
> +#define CONFIG_SYS_BR2_PRELIM ( CONFIG_SYS_CPLD_BASE \
> + | (1 << BR_PS_SHIFT) /* 8 bit port size */ \
> + | BR_V ) /* valid */
> +#define CONFIG_SYS_OR2_PRELIM ( 0xFFFF8000 /* length 32K
> */ \
> + | OR_GPCM_SCY_4 \
> + | OR_GPCM_EHTR)
> + /* 0xFFFF8042 */
> +
> +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_CPLD_BASE
> +#define CONFIG_SYS_LBLAWAR2_PRELIM 0x8000000E /* 32KB */
same here.
> +/*
> + * Fake PCIE2 definitions: there is no PCIE2 on this board but the code
> + * in arch/powerpc/cpu/mpc83xx/pcie.c doesn't compile without this
> + */
so fix the code there instead.
Kim
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