[v2, 09/11] mmc: fsl_esdhc: fix eMMC HS400 stability issue

[Yangbo Lu]

There was a fix-up for eMMC HS400 stability issue in Linux.

Patch link:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
commit/?id=58d0bf843b49fa99588ac9f85178bd8dfd651b53

Description:
Currently only LX2160A eSDHC supports eMMC HS400. According to
a large number of tests, eMMC HS400 failed to work at 150MHz,
and for a few boards failed to work at 175MHz. But eMMC HS400
worked fine on 200MHz. We hadn't found the root cause but
setting eSDHC_DLLCFG0[DLL_FREQ_SEL] = 0 using slow delay chain
seemed to resovle this issue. Let's use this as fixup for now.

Introduce the fix-up in u-boot since the issue could be reproduced
in u-boot too.

Signed-off-by: Yangbo Lu <yangbo...@nxp.com>
---
Changes for v2:
        - Added this patch.
---
 drivers/mmc/fsl_esdhc.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 8999b74..0879739 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -622,7 +622,10 @@ static void esdhc_set_timing(struct fsl_esdhc_priv *priv, 
enum bus_mode mode)
                esdhc_setbits32(&regs->sdclkctl, CMD_CLK_CTL);
                esdhc_clock_control(priv, true);
 
-               esdhc_setbits32(&regs->dllcfg0, DLL_ENABLE | DLL_FREQ_SEL);
+               if (priv->clock == 200000000)
+                       esdhc_setbits32(&regs->dllcfg0, DLL_FREQ_SEL);
+
+               esdhc_setbits32(&regs->dllcfg0, DLL_ENABLE);
                esdhc_setbits32(&regs->tbctl, HS400_WNDW_ADJUST);
 
                esdhc_clock_control(priv, false);
-- 
2.7.4