On Thu, Jun 18, 2020 at 04:05:21PM -0300, Fabio Estevam wrote:

> The clock ouput frequency is calculated incorrectly for AR8035 due to
> wrong masking of priv->clk_25m_reg and priv->clk_25m_mask.
> 
> This same issue has been already fixed in the kernel by:
> 
> commit b1f4c209d84057b6d40b939b6e4404854271d797
> Author: Oleksij Rempel <o.rem...@pengutronix.de>
> Date:   Wed Apr 1 11:57:32 2020 +0200
> 
>     net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035
> 
>     The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set
>     for the values that comprise the fields, not zero-bits-set.
> 
>     This patch fixes the clock frequency configuration for ATH8030 and
>     ATH8035 Atheros PHYs by removing the erroneous "~".
> 
>     To reproduce this bug, configure the PHY  with the device tree binding
>     "qca,clk-out-frequency" and remove the machine specific PHY fixups.
> 
>     Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding")
>     Signed-off-by: Oleksij Rempel <o.rem...@pengutronix.de>
>     Reported-by: Russell King <rmk+ker...@armlinux.org.uk>
>     Reviewed-by: Russell King <rmk+ker...@armlinux.org.uk>
>     Tested-by: Russell King <rmk+ker...@armlinux.org.uk>
>     Signed-off-by: David S. Miller <da...@davemloft.net>
> 
> Apply the same fix in the U-Boot driver.
> 
> Tested on a i.MX6 Hummingboard.
> 
> Signed-off-by: Fabio Estevam <feste...@gmail.com>
> Reviewed-by: Michael Walle <mich...@walle.cc>

Tested-by: Tom Rini <tr...@konsulko.com>

-- 
Tom

Attachment: signature.asc
Description: PGP signature

Reply via email to