Hi Marri, On Wednesday 01 September 2010 04:11:14 tma...@apm.com wrote: > From: Tirumala Marri <tma...@apm.com> > > APM82XXX is a new line of SoCs which are derivatives of > PPC44X family of processors. > > This patch adds support of CPU, cache, > tlb, 32k ocm, bootstraps, PLB AHB bus, DDR and > Some common register definitions.
Please find some comments below. <snip> > diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h > b/arch/powerpc/include/asm/ppc4xx-sdram.h index 4ec1ef8..a6cdace 100644 > --- a/arch/powerpc/include/asm/ppc4xx-sdram.h > +++ b/arch/powerpc/include/asm/ppc4xx-sdram.h > @@ -292,7 +292,7 @@ > */ > #if defined(CONFIG_440SPE) || \ > defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ > - defined(CONFIG_460SX) > + defined(CONFIG_460SX) || defined(CONFIG_APM82XXX) > #define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */ > #define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & > 0xFFE00000)) #define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & > 0xFFE00000) << 2) @@ -322,6 +322,7 @@ > * Revisit this file to check if all these 405EX defines are correct and > * can be used in the common 44x_spd_ddr2 code as well. sr, 2008-06-02 > */ > +#define SDRAM_MBXCF_BASE_ENCODE(n) (((n) & 0xFFC00000) >> 3) It seems to me, that you are adding this to the 405EX part of the header. Please re-check if this is correct. > #define SDRAM_RXBAS_SDSZ_MASK PPC_REG_VAL(19, 0xF) > #define SDRAM_RXBAS_SDSZ_4MB PPC_REG_VAL(19, 0x0) > #define SDRAM_RXBAS_SDSZ_8MB PPC_REG_VAL(19, 0x1) > @@ -346,6 +347,18 @@ > #define SDRAM_RXBAS_SDSZ_2048 SDRAM_RXBAS_SDSZ_2048MB > #define SDRAM_RXBAS_SDSZ_4096 SDRAM_RXBAS_SDSZ_4096MB > #define SDRAM_RXBAS_SDSZ_8192 SDRAM_RXBAS_SDSZ_8192MB > +#define SDRAM_RXBAS_SDAM_MODE0 PPC_REG_VAL(23, 0x0) > +#define SDRAM_RXBAS_SDAM_MODE1 PPC_REG_VAL(23, 0x1) > +#define SDRAM_RXBAS_SDAM_MODE2 PPC_REG_VAL(23, 0x2) > +#define SDRAM_RXBAS_SDAM_MODE3 PPC_REG_VAL(23, 0x3) > +#define SDRAM_RXBAS_SDAM_MODE4 PPC_REG_VAL(23, 0x4) > +#define SDRAM_RXBAS_SDAM_MODE5 PPC_REG_VAL(23, 0x5) > +#define SDRAM_RXBAS_SDAM_MODE6 PPC_REG_VAL(23, 0x6) > +#define SDRAM_RXBAS_SDAM_MODE7 PPC_REG_VAL(23, 0x7) > +#define SDRAM_RXBAS_SDAM_MODE8 PPC_REG_VAL(23, 0x8) > +#define SDRAM_RXBAS_SDAM_MODE9 PPC_REG_VAL(23, 0x9) > +#define SDRAM_RXBAS_SDBE_DISABLE PPC_REG_VAL(31, 0x0) > +#define SDRAM_RXBAS_SDBE_ENABLE PPC_REG_VAL(31, 0x1) Again, this is the 405EX part. Please fix and resubmit. Thanks. Cheers, Stefan -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
