On 6/10/20 10:16 PM, Tom Rini wrote: [...] > configs/socfpga_dbm_soc1_defconfig | 1 + > configs/socfpga_de0_nano_soc_defconfig | 1 + > configs/socfpga_de10_nano_defconfig | 1 + > configs/socfpga_de1_soc_defconfig | 1 +
I don't think those de*_soc boards have a SPI NOR at all. And I'm also afraid that enabling this will make those boards overflow SPL size limits.
