From: Jacky Bai <ping....@nxp.com>
There is no DDR_SS_GPR0 exits on i.MX8MN, so skip setting
this register on i.MX8MN.
Signed-off-by: Jacky Bai <ping....@nxp.com>
Signed-off-by: Peng Fan <peng....@nxp.com>
---
drivers/ddr/imx/imx8m/ddr_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c
index af8c1427d2..ba5ae05035 100644
--- a/drivers/ddr/imx/imx8m/ddr_init.c
+++ b/drivers/ddr/imx/imx8m/ddr_init.c
@@ -73,7 +73,7 @@ int ddr_init(struct dram_timing_info *dram_timing)
/* if ddr type is LPDDR4, do it */
tmp = reg32_read(DDRC_MSTR(0));
- if (tmp & (0x1 << 5))
+ if (tmp & (0x1 << 5) && !is_imx8mn())
reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */
/* determine the initial boot frequency */
--
2.16.4
