Hi Pragnesh, > -----Original Message----- > From: Pragnesh Patel <pragnesh.pa...@sifive.com> > Sent: Wednesday, May 27, 2020 8:10 PM > To: Sagar Kadam <sagar.ka...@sifive.com>; u-boot@lists.denx.de; > r...@andestech.com; lu...@denx.de > Cc: ja...@amarulasolutions.com; bmeng...@gmail.com; > sean...@gmail.com > Subject: RE: [PATCH v2 4/4] riscv: cpu: check and append L1 cache to cpu > features > > Hi Sagar, > > >-----Original Message----- > >From: Sagar Kadam <sagar.ka...@sifive.com> > >Sent: 26 May 2020 22:39 > >To: u-boot@lists.denx.de; r...@andestech.com; lu...@denx.de > >Cc: ja...@amarulasolutions.com; bmeng...@gmail.com; Pragnesh Patel > ><pragnesh.pa...@sifive.com>; sean...@gmail.com; Sagar Kadam > ><sagar.ka...@sifive.com> > >Subject: [PATCH v2 4/4] riscv: cpu: check and append L1 cache to cpu > >features > > > >All cpu cores within FU540-C000 having split I/D caches. > >Set the L1 feature bit using the i-cache-size as one of the property > >from > > s/L1 feature/L1 cache feature
Ok. Will update > > >device tree indicating that L1 cache is present on the cpu core. > > > >=> cpu detail > > 0: cpu@0 rv64imac > > ID = 0, freq = 999.100 MHz: L1 cache > > 1: cpu@1 rv64imafdc > > ID = 1, freq = 999.100 MHz: L1 cache, MMU > > 2: cpu@2 rv64imafdc > > ID = 2, freq = 999.100 MHz: L1 cache, MMU > > 3: cpu@3 rv64imafdc > > ID = 3, freq = 999.100 MHz: L1 cache, MMU > > 4: cpu@4 rv64imafdc > > ID = 4, freq = 999.100 MHz: L1 cache, MMU > > > >Signed-off-by: Sagar Shrikant Kadam <sagar.ka...@sifive.com> > > Reviewed-by: Pragnesh Patel <pragnesh.pa...@sifive.com> Thanks for the review's BR, Sagar Kadam
