Using PIC TFRR register for post word load/store for generic.
Fix post_word_store, post_word_load offset for mpc85xx with cpm
Signed-off-by: York Sun <york...@freescale.com>
---
arch/powerpc/cpu/mpc85xx/commproc.c | 4 ++--
arch/powerpc/cpu/mpc85xx/cpu.c | 17 +++++++++++++++++
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/commproc.c
b/arch/powerpc/cpu/mpc85xx/commproc.c
index f0fd1cb..1671b5e 100644
--- a/arch/powerpc/cpu/mpc85xx/commproc.c
+++ b/arch/powerpc/cpu/mpc85xx/commproc.c
@@ -189,7 +189,7 @@ m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int
pinsel)
void post_word_store (ulong a)
{
volatile ulong *save_addr =
- (volatile ulong *)(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR);
+ (volatile ulong *)(CONFIG_SYS_MPC85xx_CPM_ADDR +
CPM_POST_WORD_ADDR);
*save_addr = a;
}
@@ -197,7 +197,7 @@ void post_word_store (ulong a)
ulong post_word_load (void)
{
volatile ulong *save_addr =
- (volatile ulong *)(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR);
+ (volatile ulong *)(CONFIG_SYS_MPC85xx_CPM_ADDR +
CPM_POST_WORD_ADDR);
return *save_addr;
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 634a0cd..9f3aa99 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -286,6 +286,23 @@ void mpc85xx_reginfo(void)
print_lbc_regs();
}
+#ifdef CONFIG_POST
+
+__attribute__((weak))
+void post_word_store(ulong a)
+{
+ void *save_addr = (void *)(CONFIG_SYS_POST_WORD_ADDR);
+ out_be32(save_addr, a);
+}
+__attribute__((weak))
+ulong post_word_load(void)
+{
+ void *save_addr = (void *)(CONFIG_SYS_POST_WORD_ADDR);
+ return in_be32(save_addr);
+}
+
+#endif /* CONFIG_POST */
+
#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
/* Board-specific functions defined in each board's ddr.c */
--
1.7.0.4
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