Hi Stefan:
Our legal is out at the moment. Why is this an issue, since it is
on many of the files in U-Boot. Our legal indicated without the
statement the Copyright would not stand.
Thanks
Feng
>> +# Copyright (c) 2010, Applied Micro Circuits Corporation
>> +# All rights reserved. Tirumala R Marri <tma...@apm.com>
>
> IIRC, then this statement "All rights reserved" interferes with the GPL.
> Please remove it from all your files.
>
>> +#
>> +# See file CREDITS for list of people who contributed to this
>> +# project.
>> +#
>> +# This program is free software; you can redistribute it and/or
>> +# modify it under the terms of the GNU General Public License as
>> +# published by the Free Software Foundation; either version 2 of
>> +# the License, or (at your option) any later version.
>> +#
>> +# This program is distributed in the hope that it will be useful,
>> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
>> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> +# GNU General Public License for more details.
>> +#
>> +# You should have received a copy of the GNU General Public License
>> +# along with this program; if not, write to the Free Software
>> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> +# MA 02111-1307 USA
>> +#
>> +
>> +include $(TOPDIR)/config.mk
>> +
>> +LIB = $(obj)lib$(BOARD).a
>> +
>> +COBJS-y := $(BOARD).o
>> +SOBJS := init.o
>> +
>> +COBJS := $(COBJS-y)
>> +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
>> +OBJS := $(addprefix $(obj),$(COBJS))
>> +SOBJS := $(addprefix $(obj),$(SOBJS))
>> +
>> +$(LIB): $(OBJS) $(SOBJS)
>> + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
>> +
>> +clean:
>> + rm -f $(SOBJS) $(OBJS)
>> +
>> +distclean: clean
>> + rm -f $(LIB) core *.bak $(obj).depend
>> +
>> +#########################################################################
>> +
>> +# defines $(obj).depend target
>> +include $(SRCTREE)/rules.mk
>> +
>> +sinclude $(obj).depend
>> +
>> +#########################################################################
>> diff --git a/board/amcc/bluestone/bluestone.c
>> b/board/amcc/bluestone/bluestone.c new file mode 100644
>> index 0000000..b13e84a
>> --- /dev/null
>> +++ b/board/amcc/bluestone/bluestone.c
>> @@ -0,0 +1,213 @@
>> +/*
>> + * Bluestone board support
>> + *
>> + * Copyright (c) 2010, Applied Micro Circuits Corporation
>> + * All rights reserved. Tirumala R Marri <tma...@apm.com>
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> + * MA 02111-1307 USA
>> + */
>> +
>> +#include <common.h>
>> +#include <ppc440.h>
>> +#include <libfdt.h>
>> +#include <fdt_support.h>
>> +#include <i2c.h>
>> +#include <asm/processor.h>
>> +#include <asm/io.h>
>> +#include <asm/mmu.h>
>> +#include <asm/gpio.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +#define SDR_AHB_CFG 0x370
>
> Starting here...
>
>> +/* Define Boot devices */
>> +#define BOOT_FROM_8BIT_SRAM 0x00
>> +#define BOOT_FROM_8BIT_SRAM_FULL_ADDR 0x01
>> +#define BOOT_FROM_8BIT_NAND 0x02
>> +#define BOOT_FROM_8BIT_NOR 0x03
>> +#define BOOT_FROM_8BIT_NOR_FULL_ADDR 0x04
>> +#define BOOT_DEVICE_UNKNOWN 0xff
>> +
>> +#define APM82161_MASK (u32)(0x1 << 21)
>> +
>> +/* NOR Flash */
>> +#define EBC_BXAP_NOR (EBC_BXAP_BME_DISABLED | \
>> + EBC_BXAP_TWT_ENCODE(64) | \
>> + EBC_BXAP_BCE_DISABLE | \
>> + EBC_BXAP_BCT_2TRANS | \
>> + EBC_BXAP_CSN_ENCODE(1) | \
>> + EBC_BXAP_OEN_ENCODE(2) | \
>> + EBC_BXAP_WBN_ENCODE(2) | \
>> + EBC_BXAP_WBF_ENCODE(2) | \
>> + EBC_BXAP_TH_ENCODE(7) | \
>> + EBC_BXAP_SOR_DELAYED | \
>> + EBC_BXAP_BEM_WRITEONLY | \
>> + EBC_BXAP_PEN_DISABLED)
>> +/* Peripheral Bank Configuration Register - EBC_BxCR */
>> +#define EBC_BXCR_8BIT_NOR \
>> + (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
>> + EBC_BXCR_BS_1MB | \
>> + EBC_BXCR_BU_RW | \
>> + EBC_BXCR_BW_8BIT)
>> +
>> +#define EBC_BXCR_8BIT_SRAM \
>> + (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_EXTSRAM_BASE) | \
>> + EBC_BXCR_BS_1MB | \
>> + EBC_BXCR_BU_RW | \
>> + EBC_BXCR_BW_8BIT)
>
> ... till here. Why do you add these defines to this C file? These
> should be located in the general header files (ppc440.h) and/or
> the board config header.
>
>> +/*
>> + * Get bootdevice information and
>> + * setup EBC configuration
>> + * NOTE: Assume that I2C had been initialized
>> + */
>> +int bootdevice_selected(void)
>> +{
>> + unsigned long rl;
>> + unsigned long bootstrap_settings;
>> + int computed_boot_device = BOOT_DEVICE_UNKNOWN;
>> +
>> + mfsdr(SDR0_SDSTP1, bootstrap_settings);
>> + rl = SDR_SDSTP1_RL_DECODE(bootstrap_settings);
>> + if (rl == SDR_SDSTP1_RL_EBC) /* Boot device is NOR */
>> + computed_boot_device = BOOT_FROM_8BIT_NOR;
>> + else if (rl == SDR_SDSTP1_RL_NDFC)
>> + computed_boot_device = BOOT_FROM_8BIT_NAND;
>> + return computed_boot_device;
>> +}
>> +
>> +void reconfigure_EBC(int computed_boot_device)
>
> Don't use upper-case or camel-case for function names.
>
>> +{
>> + switch (computed_boot_device) {
>> + case BOOT_FROM_8BIT_NOR:
>> + /*
>> + * CS0: NOR
>> + */
>> + /* Configure EBC CS0 - Nor Flash 1MBx8 */
>> + mtebc(PB0AP, EBC_BXAP_NOR);
>> + mtebc(PB0CR, EBC_BXCR_8BIT_NOR);
>> + break;
>> + case BOOT_FROM_8BIT_NOR_FULL_ADDR:
>> + /*
>> + * CS0: NOR
>> + * CS1: x
>> + * CS2: x
>> + */
>> + /* Configure EBC CS0 - Nor Flash 1MBx8 */
>> + mtebc(PB0AP, EBC_BXAP_NOR);
>> + mtebc(PB0CR, EBC_BXCR_8BIT_NOR);
>> + break;
>
> Hmmm. This looks wrong. In both cases the same values are written to the EBC
> register. Please check again if this is want you really want.
>
>> + default:
>> + break;
>> + }
>> +}
>> +
>> +int board_early_init_f(void)
>> +{
>> + /*
>> + * Setup the interrupt controller polarities, triggers, etc.
>> + */
>> + mtdcr(UIC0SR, 0xffffffff); /* clear all */
>> + mtdcr(UIC0ER, 0x00000000); /* disable all */
>> + mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
>> + mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
>> + mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
>> + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
>> + mtdcr(UIC0SR, 0xffffffff); /* clear all */
>> +
>> + mtdcr(UIC1SR, 0xffffffff); /* clear all */
>> + mtdcr(UIC1ER, 0x00000000); /* disable all */
>> + mtdcr(UIC1CR, 0x00000000); /* all non-critical */
>> + mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
>> + mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
>> + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
>> + mtdcr(UIC1SR, 0xffffffff); /* clear all */
>> +
>> + mtdcr(UIC2SR, 0xffffffff); /* clear all */
>> + mtdcr(UIC2ER, 0x00000000); /* disable all */
>> + mtdcr(UIC2CR, 0x00000000); /* all non-critical */
>> + mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
>> + mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
>> + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
>> + mtdcr(UIC2SR, 0xffffffff); /* clear all */
>> +
>> + mtdcr(UIC3SR, 0xffffffff); /* clear all */
>> + mtdcr(UIC3ER, 0x00000000); /* disable all */
>> + mtdcr(UIC3CR, 0x00000000); /* all non-critical */
>> + mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
>> + mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
>> + mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
>> + mtdcr(UIC3SR, 0xffffffff); /* clear all */
>> +
>> + /*
>> + * Configure PFC (Pin Function Control) registers
>> + * UART0: 2 pins
>> + */
>> + mtsdr(SDR0_PFC1, 0x0000000);
>> +
>> + return 0;
>> +}
>> +
>> +int checkboard(void)
>> +{
>> + char *s = getenv("serial#");
>> +
>> + printf("Board: Bluestone Evaluation Board");
>> +
>> + if (s != NULL) {
>> + puts(", serial# ");
>> + puts(s);
>> + }
>> + putc('\n');
>> +
>> + return 0;
>> +}
>> +
>> +int board_early_init_r(void)
>> +{
>> + u32 bootdevice;
>> +
>> + /*
>> + * Clear potential errors resulting from auto-calibration.
>> + * If not done, then we could get an interrupt later on when
>> + * exceptions are enabled.
>> + */
>> + set_mcsr(get_mcsr());
>> +
>> + /* Reconfigure EBC here */
>> + bootdevice = bootdevice_selected();
>> + reconfigure_EBC(bootdevice);
>
> Please explain why the EBC needs to be reconfigured at this stage.
>
>> +
>> + return 0;
>> +}
>> +
>> +int misc_init_r(void)
>> +{
>> + u32 sdr0_srst1 = 0;
>
> Add empty line here.
>
>> + /* Setup PLB4-AHB bridge based on the system address map */
>> + mtdcr(AHB_TOP, 0x8000004B);
>> + mtdcr(AHB_BOT, 0x8000004B);
>
> Again, add empty line.
>
>> + /*
>> + * The AHB Bridge core is held in reset after power-on or reset
>> + * so enable it now
>> + */
>> + mfsdr(SDR0_SRST1, sdr0_srst1);
>> + sdr0_srst1 &= ~SDR0_SRST1_AHB;
>> + mtsdr(SDR0_SRST1, sdr0_srst1);
>> +
>> + return 0;
>> +}
>> diff --git a/board/amcc/bluestone/config.mk
>> b/board/amcc/bluestone/config.mk new file mode 100644
>> index 0000000..dca5a9a
>> --- /dev/null
>> +++ b/board/amcc/bluestone/config.mk
>> @@ -0,0 +1,40 @@
>> +#
>> +# Copyright (c) 2010, Applied Micro Circuits Corporation
>> +# All rights reserved. Tirumala R Marri <tma...@apm.com>
>> +#
>> +# See file CREDITS for list of people who contributed to this
>> +# project.
>> +#
>> +# This program is free software; you can redistribute it and/or
>> +# modify it under the terms of the GNU General Public License as
>> +# published by the Free Software Foundation; either version 2 of
>> +# the License, or (at your option) any later version.
>> +#
>> +# This program is distributed in the hope that it will be useful,
>> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
>> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> +# GNU General Public License for more details.
>> +#
>> +# You should have received a copy of the GNU General Public License
>> +# along with this program; if not, write to the Free Software
>> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> +# MA 02111-1307 USA
>> +#
>> +# Applied Micro APM82XXX Evaluation board.
>> +#
>> +
>> +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
>> +
>> +ifndef TEXT_BASE
>> +TEXT_BASE = 0xFFFA0000
>> +endif
>> +
>> +PLATFORM_CPPFLAGS += -DCONFIG_440=1
>> +
>> +ifeq ($(debug),1)
>> +PLATFORM_CPPFLAGS += -DDEBUG
>> +endif
>> +
>> +ifeq ($(dbcr),1)
>> +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
>> +endif
>> diff --git a/board/amcc/bluestone/init.S b/board/amcc/bluestone/init.S
>> new file mode 100644
>> index 0000000..a74d75a
>> --- /dev/null
>> +++ b/board/amcc/bluestone/init.S
>> @@ -0,0 +1,55 @@
>> +/*
>> + * Copyright (c) 2010, Applied Micro Circuits Corporation
>> + * All rights reserved. Tirumala R Marri <tma...@apm.com>
>> + *
>> + * See file CREDITS for list of people who contributed to this
>> + * project.
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> + * MA 02111-1307 USA
>> + */
>> +
>> +#include <ppc_asm.tmpl>
>> +#include <config.h>
>> +#include <asm/mmu.h>
>> +
>> +/*************************************************************************
>> * + * TLB TABLE
>> + *
>> + * This table is used by the cpu boot code to setup the initial tlb
>> + * entries. Rather than make broad assumptions in the cpu source tree,
>> + * this table lets each board set things up however they like.
>> + *
>> + * Pointer to the table is returned in r1
>> + *
>> +
>> *************************************************************************/
>> + .section .bootpg,"ax"
>> + .globl tlbtab
>> +
>> +tlbtab:
>> + tlbtab_start
>> +
>> + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
>> + tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR,
>> + 0, AC_R|AC_W|AC_X|SA_G)
>> +
>> + /* TLB-entry for OCM */
>> + tlbentry(CONFIG_SYS_OCM_BASE, SZ_64K, 0x00040000, 4,
>> + AC_R|AC_W|AC_X|SA_I)
>> +
>> + /* TLB-entry for Local Configuration registers => peripherals */
>> + tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K,
>> + CONFIG_SYS_PERIPHERAL_BASE, 4, AC_R|AC_W|AC_X|SA_G|
> SA_I)
>
> Recently I added some macros to make this TLB table a bit easier:
>
> AC_RWX etc. Please use those macros here.
>
>> + tlbtab_end
>> diff --git a/include/configs/bluestone.h b/include/configs/bluestone.h
>> new file mode 100644
>> index 0000000..44b2264
>> --- /dev/null
>> +++ b/include/configs/bluestone.h
>> @@ -0,0 +1,218 @@
>> +/*
>> + * bluestone.h - configuration for Blouestone (APM82XXX)
>> + *
>> + * Copyright (c) 2010, Applied Micro Circuits Corporation
>> + * All rights reserved. Tirumala R Marri <tma...@apm.com>
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> + * MA 02111-1307 USA
>> + */
>> +
>> +#ifndef __CONFIG_H
>> +#define __CONFIG_H
>> +
>> +/*
>> + * High Level Configuration Options
>> + */
>> +#define CONFIG_APM82181 1 /* Specific APM82XXX */
>> +#define CONFIG_APM82XXX 1 /* APM82XXX series */
>> +#define CONFIG_HOSTNAME bluestone
>> +
>> +#define CONFIG_440 1
>> +#define CONFIG_4xx 1 /* ... PPC4xx family */
>> +
>> +/*
>> + * Include common defines/options for all AMCC eval boards
>> + */
>> +#include "amcc-common.h"
>> +#define CONFIG_SYS_CLK_FREQ 50000000
>> +
>> +#define CONFIG_BOARD_TYPES 1 /* support board types */
>> +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
>> +#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
>> +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
>> +
>> +/*
>> + * Base addresses -- Note these are effective addresses where the
>> + * actual resources get mapped (not physical addresses)
>> + */
>> +/* EBC stuff */
>> +#define CONFIG_SYS_EXTSRAM_BASE 0xE1000000 /* 2MB */
>> +/* later mapped to this addr */
>> +#define CONFIG_SYS_FLASH_BASE 0xFFF00000
>> +#define CONFIG_SYS_FLASH_SIZE (1 << 20) /* 1MB usable
> */
>> +
>> +#define CONFIG_SYS_NAND0_ADDR 0xE4000000
>> +#define CONFIG_SYS_NAND1_ADDR 0xE5000000
>> +/* EBC Boot Space: 0xFF000000 */
>> +#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000
>> +#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 32k */
>> +#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
>> +#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal peripherals */
>> +#define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB
> peripherals*/
>> +
>> +/*
>> + * Initial RAM & stack pointer (placed in OCM)
>> + */
>> +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
>> +#define CONFIG_SYS_INIT_RAM_END (4 << 10)
>> +#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
>> +#define CONFIG_SYS_GBL_DATA_OFFSET \
>> + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
>> +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
>> +
>> +/*
>> + * Environment
>> + */
>> +/*
>> + * Define here the location of the environment variables (FLASH).
>> + */
>> +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) \
>> + && !defined(CONFIG_SRAM_U_BOOT)
>
> You don't add NAND-booting support for this board. Either include it or remove
> these NAND-booting related defines/configurations.
>
> And even more, NAND support doesn't seem to be enabled at all. Please remove
> the NAND stuff completely. This will make the patch much more clear.
>
>> +#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment
> vars */
>> +#define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */
>> +#define CONFIG_SYS_NAND_CS 1 /* NAND chip connected to CSx */
>> +#else
>> +#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment
> vars */
>> +#define CONFIG_SYS_NOR_CS 2 /* NOR chip connected to CSx */
>> +#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
>> +#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
>> +#endif
>> +
>> +#if !defined(CONFIG_NAND_U_BOOT)
>> +/* Boot from NOR, store environment to NAND */
>> +#ifdef CONFIG_ENV_IS_IN_NAND
>> +
>> +/*
>> + * Too big environment size (512KB) may cause system
>> + * hang due to out of malloc space
>> + */
>> +#define CONFIG_ENV_SIZE (64 << 10)
>> +#define CONFIG_ENV_OFFSET (2 << 20)
>> +#endif
>> +#else /* NAND boot */
>> +#ifdef CONFIG_ENV_IS_IN_NAND
>> +/*
>> + * For NAND booting the environment is embedded in the U-Boot image.
>> Please take + * look at the file board/amcc/canyonlands/u-boot-nand.lds
>> for details. + */
>> +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
>> +#define CONFIG_ENV_OFFSET \
>> + (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
>> +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
>> +#endif
>> +#endif /* !defined(CONFIG_NAND_U_BOOT) */
>> +/*
>> + * FLASH related
>> + */
>> +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
>> +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
>> +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
>> +/* Reduce the actual size of the flash */
>> +#define CONFIG_SIZE_REDUCE (3 << 20)
>> +/* Reduce the actual sectors of the flash */
>> +#define CONFIG_SECTOR_REDUCE 48
>
> What are those two defines (xxx_REDUCE)? I have never seen those before. And
> they don't seem to be referenced in your patchset either. Please remove.
>
>> +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
>> +/* max number of memory banks */
>> +#define CONFIG_SYS_MAX_FLASH_BANKS 1
>> +/* max number of sectors on one chip */
>> +#define CONFIG_SYS_MAX_FLASH_SECT 80
>> +/* Timeout for Flash Erase (in ms) */
>> +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
>> +/* Timeout for Flash Write (in ms) */
>> +#define CONFIG_SYS_FLASH_WRITE_TOUT 500
>> +/* use buffered writes (20x faster) */
>> +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
>> +/* print 'E' for empty sector on flinfo */
>> +#define CONFIG_SYS_FLASH_EMPTY_INFO
>> +#ifdef CONFIG_ENV_IS_IN_FLASH
>> +#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
>> +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE -
> CONFIG_ENV_SECT_SIZE)
>> +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment
> Sector */
>> +/* Address and size of Redundant Environment Sector */
>> +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR -
> CONFIG_ENV_SECT_SIZE)
>> +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
>> +#endif /* CONFIG_ENV_IS_IN_FLASH */
>> +/*
>> + * NAND-FLASH related
>> + */
>> +#if !defined(CONFIG_NAND_U_BOOT)
>> +#define CONFIG_SYS_MAX_NAND_DEVICE 1
>> +#define CONFIG_SYS_NAND_BASE \
>> + (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
>> +#define CONFIG_SYS_NAND_MAX_CHIPS 1
>> +#else /* NAND boot */
>> +#define CONFIG_SYS_MAX_NAND_DEVICE 1
>> +#define CONFIG_SYS_NAND_BASE \
>> + {CONFIG_SYS_NAND0_ADDR + 0/*, CONFIG_SYS_NAND1_ADDR + 1*/}
>> +#define CONFIG_SYS_NAND_MAX_CHIPS 1
>> +#define NOT_USE_FLASH
>> +#endif
>> +/* nand driver supports mutipl. chips */
>> +#define CONFIG_SYS_NAND_SELECT_DEVICE 1
>> +/*
>> + * Use 1 byte of I2C EEPROM as a flag to force SDRAM controller
>> + * to be configured as 16-bit
>> + */
>> +#define CONFIG_SDRAM_INFO_EEPROM_ADDR 0x54 /* Board specific */
>> +#define CONFIG_SDRAM16BIT_OFFSET 0x20 /* Board specific */
>
> Those two defines are not used in your patches. Please remove.
>
>> +#if !defined(CONFIG_NAND_U_BOOT)
>> +/*
>> + * NAND booting U-Boot version uses a fixed initialization, since the
>> whole + * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k
>> of boot + * code.
>> + */
>> +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
>> +#define SPD_EEPROM_ADDRESS {0x53, 0x51} /* SPD i2c spd addresses */
>> +#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration
>> */ +#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose
>> */ +#define CONFIG_DDR_ECC 1 /* with ECC support
> */
>> +#endif /* !defined(CONFIG_NAND_U_BOOT) */
>> +/*
>> + * I2C
>> + */
>> +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
>> +
>> +#define CONFIG_SYS_I2C_MULTI_EEPROMS
>> +#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
>
> Space around ">>".
>
>> +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
>> +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
>> +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Data sheet
> */
>> +/* I2C bootstrap EEPROM */
>> +#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
>> +#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
>> +#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
>
> Those defines are used be the board specific "chip_config" command. Which you
> didn't include in this patchset. Either add it or remove these defines.
>
>> +/*
>> + * Ethernet
>> + */
>> +#define CONFIG_IBM_EMAC4_V4 1
>> +#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_NONE_RGMII
>> +#define CONFIG_HAS_ETH0
>> +#define CONFIG_M88E1111_PHY
>> +/* PHY address, See schematics */
>> +#define CONFIG_PHY_ADDR 0x1f
>> +/* reset phy upon startup */
>> +#define CONFIG_PHY_RESET 1
>> +#define CONFIG_PHY_RESET_R
>
> What's CONFIG_PHY_RESET_R? Please remove.
>
>> +/* Include GbE speed/duplex detection */
>> +#define CONFIG_PHY_GIGE 1
>> +#define CONFIG_PHY_DYNAMIC_ANEG 1
>> +/*
>> + * External Bus Controller (EBC) Setup
>> + **/
>> +#define CONFIG_SYS_EBC_CFG 0xB8400000 /* EBC0_CFG */
>> +
>> +#endif /* __CONFIG_H */
>
> Please fix and resubmit. Thanks.
>
> Cheers,
> Stefan
>
> --
> DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de
> _______________________________________________
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>
--
Feng Kan
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