From: Tirumala Marri <tma...@apm.com>
This patch adds 32bit DDR2 static as well as dynamic
setting of different DRAM parameters like CAS and read/write
delays.
Signed-off-by: Tirumala R Marri <tma...@apm.com>
---
arch/powerpc/include/asm/ppc4xx-sdram.h | 25 +++++++++++++++++++------
1 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h
b/arch/powerpc/include/asm/ppc4xx-sdram.h
index 4ec1ef8..a6cdace 100644
--- a/arch/powerpc/include/asm/ppc4xx-sdram.h
+++ b/arch/powerpc/include/asm/ppc4xx-sdram.h
@@ -292,7 +292,7 @@
*/
#if defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_460SX)
+ defined(CONFIG_460SX) || defined(CONFIG_APM82XXX)
#define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */
#define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) &
0xFFE00000))
#define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2)
@@ -322,6 +322,7 @@
* Revisit this file to check if all these 405EX defines are correct and
* can be used in the common 44x_spd_ddr2 code as well. sr, 2008-06-02
*/
+#define SDRAM_MBXCF_BASE_ENCODE(n) (((n) & 0xFFC00000) >> 3)
#define SDRAM_RXBAS_SDSZ_MASK PPC_REG_VAL(19, 0xF)
#define SDRAM_RXBAS_SDSZ_4MB PPC_REG_VAL(19, 0x0)
#define SDRAM_RXBAS_SDSZ_8MB PPC_REG_VAL(19, 0x1)
@@ -346,6 +347,18 @@
#define SDRAM_RXBAS_SDSZ_2048 SDRAM_RXBAS_SDSZ_2048MB
#define SDRAM_RXBAS_SDSZ_4096 SDRAM_RXBAS_SDSZ_4096MB
#define SDRAM_RXBAS_SDSZ_8192 SDRAM_RXBAS_SDSZ_8192MB
+#define SDRAM_RXBAS_SDAM_MODE0 PPC_REG_VAL(23, 0x0)
+#define SDRAM_RXBAS_SDAM_MODE1 PPC_REG_VAL(23, 0x1)
+#define SDRAM_RXBAS_SDAM_MODE2 PPC_REG_VAL(23, 0x2)
+#define SDRAM_RXBAS_SDAM_MODE3 PPC_REG_VAL(23, 0x3)
+#define SDRAM_RXBAS_SDAM_MODE4 PPC_REG_VAL(23, 0x4)
+#define SDRAM_RXBAS_SDAM_MODE5 PPC_REG_VAL(23, 0x5)
+#define SDRAM_RXBAS_SDAM_MODE6 PPC_REG_VAL(23, 0x6)
+#define SDRAM_RXBAS_SDAM_MODE7 PPC_REG_VAL(23, 0x7)
+#define SDRAM_RXBAS_SDAM_MODE8 PPC_REG_VAL(23, 0x8)
+#define SDRAM_RXBAS_SDAM_MODE9 PPC_REG_VAL(23, 0x9)
+#define SDRAM_RXBAS_SDBE_DISABLE PPC_REG_VAL(31, 0x0)
+#define SDRAM_RXBAS_SDBE_ENABLE PPC_REG_VAL(31, 0x1)
#endif /* CONFIG_405EX */
/* The mode definitions are the same for all PPC4xx variants */
@@ -365,7 +378,7 @@
/*
* Memory controller registers
*/
-#ifdef CONFIG_405EX
+#if defined(CONFIG_405EX) || defined(CONFIG_APM82XXX)
#define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */
#define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */
#define SDRAM_BEARL 0x02 /* PLB bus error address low */
@@ -375,9 +388,9 @@
#define SDRAM_PLBOPT 0x08 /* PLB slave options */
#define SDRAM_PUABA 0x09 /* PLB upper address base */
#define SDRAM_MCSTAT 0x1F /* memory controller status */
-#else /* CONFIG_405EX */
+#else /* CONFIG_405EX || CONFIG_APM82XXX*/
#define SDRAM_MCSTAT 0x14 /* memory controller status */
-#endif /* CONFIG_405EX */
+#endif /* CONFIG_405EX || CONFIG_APM82XXX*/
#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
@@ -423,12 +436,12 @@
#define SDRAM_MEMODE 0x89 /* memory extended mode */
#define SDRAM_ECCES 0x98 /* ECC error status */
#define SDRAM_CID 0xA4 /* core ID */
-#ifndef CONFIG_405EX
+#if !defined(CONFIG_405EX) && !defined(CONFIG_APM82XXX)
#define SDRAM_RID 0xA8 /* revision ID */
#endif
#define SDRAM_FCSR 0xB0 /* feedback calibration status */
#define SDRAM_RTSR 0xB1 /* run time status tracking */
-#ifdef CONFIG_405EX
+#if defined(CONFIG_405EX) || defined(CONFIG_APM82XXX)
#define SDRAM_RID 0xF8 /* revision ID */
#endif
--
1.6.1.rc3
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