On Tue, May 19, 2020 at 12:35 PM Pragnesh Patel <pragnesh.pa...@sifive.com> wrote: > > Release ethernet clock reset once clock is initialized. > This is necessary to do as U-Boot proper needs ethernet > clock.
Better write proper commit mesaage can clear the reason for phy reset here. Sample "U-Boot ethernet phy work with FSBL flow where the phy reset is part of FSBL itself, but since SPL not touching ant ethernet phy an explicit ethernet phy required for U-Boot proper. With this change phy reset code in FSBL might not be needed or unaffected." Jagan.
