>-----Original Message----- >From: Jagan Teki <ja...@amarulasolutions.com> >Sent: 11 May 2020 14:30 >To: Pragnesh Patel <pragnesh.pa...@sifive.com> >Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra ><atish.pa...@wdc.com>; Palmer Dabbelt <palmerdabb...@google.com>; Bin >Meng <bmeng...@gmail.com>; Paul Walmsley <paul.walms...@sifive.com>; >Troy Benjegerdes <troy.benjeger...@sifive.com>; Anup Patel ><anup.pa...@wdc.com>; Sagar Kadam <sagar.ka...@sifive.com>; Rick Chen ><r...@andestech.com>; Palmer Dabbelt <pal...@sifive.com> >Subject: Re: [PATCH v8 15/21] riscv: sifive: fu540: add SPL configuration > >[External Email] Do not click links or attachments unless you recognize the >sender and know the content is safe > >On Sat, May 9, 2020 at 8:02 PM Pragnesh Patel <pragnesh.pa...@sifive.com> >wrote: >> >> Add a support for SPL which will boot from L2 LIM (0x0800_0000) and >> then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin) >> from MMC boot devices. >> >> SPL related code is leveraged from FSBL >> (https://github.com/sifive/freedom-u540-c000-bootloader.git) >> >> Signed-off-by: Pragnesh Patel <pragnesh.pa...@sifive.com> >> Reviewed-by: Bin Meng <bmeng...@gmail.com> >> Tested-by: Bin Meng <bmeng...@gmail.com> >> --- >> arch/riscv/cpu/fu540/Makefile | 4 ++ >> arch/riscv/cpu/fu540/spl.c | 23 ++++++ >> .../dts/hifive-unleashed-a00-u-boot.dtsi | 5 ++ >> arch/riscv/include/asm/arch-fu540/spl.h | 14 ++++ >> board/sifive/fu540/Kconfig | 12 +++- >> board/sifive/fu540/Makefile | 4 ++ >> board/sifive/fu540/fu540.c | 24 +++++++ >> board/sifive/fu540/spl.c | 72 +++++++++++++++++++ >> include/configs/sifive-fu540.h | 18 +++++ >> 9 files changed, 174 insertions(+), 2 deletions(-) create mode >> 100644 arch/riscv/cpu/fu540/spl.c create mode 100644 >> arch/riscv/include/asm/arch-fu540/spl.h >> create mode 100644 board/sifive/fu540/spl.c >> >> diff --git a/arch/riscv/cpu/fu540/Makefile >> b/arch/riscv/cpu/fu540/Makefile index 44700d998c..043fb961a5 100644 >> --- a/arch/riscv/cpu/fu540/Makefile >> +++ b/arch/riscv/cpu/fu540/Makefile >> @@ -3,5 +3,9 @@ >> # Copyright (C) 2020 SiFive, Inc >> # Pragnesh Patel <pragnesh.pa...@sifive.com> >> >> +ifeq ($(CONFIG_SPL_BUILD),y) >> +obj-y += spl.o >> +else >> obj-y += dram.o >> obj-y += cpu.o >> +endif >> diff --git a/arch/riscv/cpu/fu540/spl.c b/arch/riscv/cpu/fu540/spl.c >> new file mode 100644 index 0000000000..2e05d8a6e2 >> --- /dev/null >> +++ b/arch/riscv/cpu/fu540/spl.c >> @@ -0,0 +1,23 @@ >> +// SPDX-License-Identifier: GPL-2.0+ >> +/* >> + * Copyright (C) 2020 SiFive, Inc >> + * Pragnesh Patel <pragnesh.pa...@sifive.com> */ >> + >> +#include <common.h> >> +#include <dm.h> >> + >> +int soc_spl_init(void) >> +{ >> + int ret; >> + struct udevice *dev; >> + >> + /* DDR init */ >> + ret = uclass_get_device(UCLASS_RAM, 0, &dev); >> + if (ret) { >> + debug("DRAM init failed: %d\n", ret); >> + return ret; >> + } >> + >> + return 0; >> +} >> diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi >> b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi >> index 9787332bf1..37de015de6 100644 >> --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi >> +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi >> @@ -4,6 +4,7 @@ >> */ >> >> #include "fu540-c000-u-boot.dtsi" >> +#include "fu540-hifive-unleashed-a00-sdram-ddr4.dtsi" >> >> / { >> aliases { >> @@ -26,3 +27,7 @@ >> u-boot,dm-spl; >> }; >> }; >> + >> +&gpio { >> + u-boot,dm-spl; >> +}; >> diff --git a/arch/riscv/include/asm/arch-fu540/spl.h >> b/arch/riscv/include/asm/arch-fu540/spl.h >> new file mode 100644 >> index 0000000000..0c188be747 >> --- /dev/null >> +++ b/arch/riscv/include/asm/arch-fu540/spl.h >> @@ -0,0 +1,14 @@ >> +/* SPDX-License-Identifier: GPL-2.0+ */ >> +/* >> + * Copyright (C) 2020 SiFive, Inc. >> + * >> + * Authors: >> + * Pragnesh Patel <pragnesh.pa...@sifve.com> >> + */ >> + >> +#ifndef _SPL_SIFIVE_H >> +#define _SPL_SIFIVE_H >> + >> +int soc_spl_init(void); >> + >> +#endif /* _SPL_SIFIVE_H */ >> diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig >> index d41c305227..4a77a2a37b 100644 >> --- a/board/sifive/fu540/Kconfig >> +++ b/board/sifive/fu540/Kconfig >> @@ -7,18 +7,26 @@ config SYS_VENDOR >> default "sifive" >> >> config SYS_CPU >> - default "generic" >> + default "fu540" >> >> config SYS_CONFIG_NAME >> default "sifive-fu540" >> >> config SYS_TEXT_BASE >> + default 0x80200000 if SPL >> default 0x80000000 if !RISCV_SMODE >> default 0x80200000 if RISCV_SMODE >> >> +config SPL_TEXT_BASE >> + default 0x08000000 >> + >> +config SPL_OPENSBI_LOAD_ADDR >> + default 0x80000000 >> + >> config BOARD_SPECIFIC_OPTIONS # dummy >> def_bool y >> - select GENERIC_RISCV >> + select SIFIVE_FU540 >> + select SUPPORT_SPL >> select RAM >> select SPL_RAM if SPL >> imply CMD_DHCP >> diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile >> index 6e1862c475..b05e2f5807 100644 >> --- a/board/sifive/fu540/Makefile >> +++ b/board/sifive/fu540/Makefile >> @@ -3,3 +3,7 @@ >> # Copyright (c) 2019 Western Digital Corporation or its affiliates. >> >> obj-y += fu540.o >> + >> +ifdef CONFIG_SPL_BUILD >> +obj-y += spl.o >> +endif >> diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c >> index 540638c919..d05529a86b 100644 >> --- a/board/sifive/fu540/fu540.c >> +++ b/board/sifive/fu540/fu540.c >> @@ -11,6 +11,7 @@ >> #include <linux/delay.h> >> #include <linux/io.h> >> #include <misc.h> >> +#include <spl.h> >> >> /* >> * This define is a value used for error/unknown serial. >> @@ -114,3 +115,26 @@ int board_init(void) >> >> return 0; >> } >> + >> +#ifdef CONFIG_SPL >> +void board_boot_order(u32 *spl_boot_list) { >> + u8 i; >> + u32 boot_devices[] = { >> +#ifdef CONFIG_SPL_MMC_SUPPORT >> + BOOT_DEVICE_MMC1, >> +#endif >> + }; >> + >> + for (i = 0; i < ARRAY_SIZE(boot_devices); i++) >> + spl_boot_list[i] = boot_devices[i]; } #endif > >Board has static jumpers to set boot mode, so boot order won't be possible so >add spl_boot_device by assigning MMC boot device for now.
Will update in v9, thanks for the review. > >Otherwise, > >Reviewed-by: Jagan Teki <ja...@amarulasolutions.com>
