Hi Jim,
On Fri, 2020-05-08 at 10:25 -0400, Jim Quinlan wrote:
> > > > +static int brcm_pcie_probe(struct udevice *dev)
> > > > +{
> > > > + struct udevice *ctlr = pci_get_controller(dev);
> > > > + struct pci_controller *hose = dev_get_uclass_priv(ctlr);
> > > > + struct brcm_pcie *pcie = dev_get_priv(dev);
> > > > + void __iomem *base = pcie->base;
> > > > + bool ssc_good = false;
> > > > + int num_out_wins = 0;
> > > > + u64 rc_bar2_offset, rc_bar2_size;
> > > > + unsigned int scb_size_val;
> > > > + int i, ret;
> > > > + u16 nlw, cls, lnksta;
> > > > + u32 tmp;
> > > > +
> > > > + /* Reset the bridge */
> > > > + brcm_pcie_bridge_sw_init_set(pcie, 1);
> > > > +
> > > > + udelay(150);
> > >
> > > Please add a comment as to how you chose the value, and below.
> >
> > This was picked from Jim Quinlan's original code submission:
> > https://lkml.org/lkml/2018/9/19/642
> >
> > Sadly there isn't any comment there.
>
> The bridge is being reset and then un-reset. The delay is a safety
> precaution to preclude the reset signal from looking like a glitch.
> BTW, what is the context here? Aren't these patches already upstream?This is the submission for u-boot. Regards, Nicolas
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