Hi Jagan, >-----Original Message----- >From: Jagan Teki <ja...@amarulasolutions.com> >Sent: 02 May 2020 21:21 >To: Pragnesh Patel <pragnesh.pa...@sifive.com> >Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra ><atish.pa...@wdc.com>; Palmer Dabbelt <palmerdabb...@google.com>; Bin >Meng <bmeng...@gmail.com>; Paul Walmsley <paul.walms...@sifive.com>; >Troy Benjegerdes <troy.benjeger...@sifive.com>; Anup Patel ><anup.pa...@wdc.com>; Sagar Kadam <sagar.ka...@sifive.com>; Rick Chen ><r...@andestech.com>; Tero Kristo <t-kri...@ti.com>; Simon Glass ><s...@chromium.org>; Adam Ford <aford...@gmail.com>; Eugen Hristev ><eugen.hris...@microchip.com>; Peng Fan <peng....@nxp.com>; Finley Xiao ><finley.x...@rock-chips.com>; Kever Yang <kever.y...@rock-chips.com> >Subject: Re: [PATCH v7 01/22] misc: add driver for the SiFive otp controller > >[External Email] Do not click links or attachments unless you recognize the >sender and know the content is safe > >On Sat, May 2, 2020 at 9:12 PM Pragnesh Patel <pragnesh.pa...@sifive.com> >wrote: >> >> Hi Jagan, >> >> >-----Original Message----- >> >From: Jagan Teki <ja...@amarulasolutions.com> >> >Sent: 02 May 2020 21:07 >> >To: Pragnesh Patel <pragnesh.pa...@sifive.com> >> >Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra >> ><atish.pa...@wdc.com>; Palmer Dabbelt <palmerdabb...@google.com>; >Bin >> >Meng <bmeng...@gmail.com>; Paul Walmsley ><paul.walms...@sifive.com>; >> >Troy Benjegerdes <troy.benjeger...@sifive.com>; Anup Patel >> ><anup.pa...@wdc.com>; Sagar Kadam <sagar.ka...@sifive.com>; Rick >Chen >> ><r...@andestech.com>; Tero Kristo <t-kri...@ti.com>; Simon Glass >> ><s...@chromium.org>; Adam Ford <aford...@gmail.com>; Eugen Hristev >> ><eugen.hris...@microchip.com>; Peng Fan <peng....@nxp.com>; Finley >> >Xiao <finley.x...@rock-chips.com>; Kever Yang >> ><kever.y...@rock-chips.com> >> >Subject: Re: [PATCH v7 01/22] misc: add driver for the SiFive otp >> >controller >> > >> >[External Email] Do not click links or attachments unless you >> >recognize the sender and know the content is safe >> > >> >On Sat, May 2, 2020 at 3:37 PM Pragnesh Patel >> ><pragnesh.pa...@sifive.com> >> >wrote: >> >> >> >> Added a misc driver to handle OTP memory in SiFive SoCs. >> >> >> >> Signed-off-by: Pragnesh Patel <pragnesh.pa...@sifive.com> >> >> --- >> >> drivers/misc/Kconfig | 7 + >> >> drivers/misc/Makefile | 1 + >> >> drivers/misc/sifive-otp.c | 273 >> >> ++++++++++++++++++++++++++++++++++++++ >> >> 3 files changed, 281 insertions(+) create mode 100644 >> >> drivers/misc/sifive-otp.c >> >> >> >> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index >> >> 766402745d..03464f1010 100644 >> >> --- a/drivers/misc/Kconfig >> >> +++ b/drivers/misc/Kconfig >> >> @@ -68,6 +68,13 @@ config ROCKCHIP_OTP >> >> addressing and a length or through child-nodes that are >> >> generated >> >> based on the e-fuse map retrieved from the DTS. >> >> >> >> +config SIFIVE_OTP >> >> + bool "SiFive eMemory OTP driver" >> >> + depends on RISCV && MISC >> > >> >This can be something like this. >> > >> >config SIFIVE_OTP >> > bool "SiFive eMemory OTP driver" >> > depends on SIFIVE_FU540 >> >> This config option is not FU540 specific but it's for all SiFive SoCs. > >Well RISCV is not SIFIVE, better add SIFIVE_FU540 as of now if you have more >SoC's in future will update by adding one more or add new symbol SIFIVE.
IMHO it's better not to make it SoC specific, Board Kconfig file will imply this option if needed. This is something we follow for FU540. SIFIVE_OTP is depends on SIFIVE SoCs and all SIFIVE SoCs are RISCV specific that's why I added depends on RISCV. > >Jagan.
