On Sat, May 2, 2020 at 3:38 PM Pragnesh Patel <pragnesh.pa...@sifive.com> wrote: > > Add ddr clock release reset and ehternet clock initialization for > SPL
Why ethernet still require for SPL? Jagan.
- RE: [PATCH v7 07/22] sifive: dts: fu540: Add DDR c... Pragnesh Patel
- [PATCH v7 13/22] riscv: cpu: fu540: Add support for cpu fu5... Pragnesh Patel
- [PATCH v7 10/22] clk: sifive: fu540-prci: ddr and ethernet ... Pragnesh Patel
- Re: [PATCH v7 10/22] clk: sifive: fu540-prci: ddr and ... Bin Meng
- RE: [PATCH v7 10/22] clk: sifive: fu540-prci: ddr ... Pragnesh Patel
- RE: [PATCH v7 10/22] clk: sifive: fu540-prci: ... Pragnesh Patel
- Re: [PATCH v7 10/22] clk: sifive: fu540-prci: ddr and ... Jagan Teki
- RE: [PATCH v7 10/22] clk: sifive: fu540-prci: ddr ... Pragnesh Patel
- Re: [PATCH v7 10/22] clk: sifive: fu540-prci: ... Jagan Teki
- RE: [PATCH v7 10/22] clk: sifive: fu540-pr... Pragnesh Patel
- [PATCH v7 09/22] clk: sifive: fu540-prci: Add clock enable ... Pragnesh Patel
- [PATCH v7 17/22] riscv: sifive: fu540: add SPL configuratio... Pragnesh Patel
- [PATCH v7 16/22] riscv: Enable cpu clock if it is present Pragnesh Patel
