>-----Original Message-----
>From: U-Boot <u-boot-boun...@lists.denx.de> On Behalf Of
>andy.t...@nxp.com
>Sent: Thursday, March 19, 2020 2:18 PM
>To: Priyanka Jain <priyanka.j...@nxp.com>
>Cc: Sudhanshu Gupta <sudhanshu.gu...@nxp.com>; u-boot@lists.denx.de;
>Andy Tang <andy.t...@nxp.com>; Vabhav Sharma
><vabhav.sha...@nxp.com>
>Subject: [PATCH 1/4] board: freescale: ls1028a: mux changes for lpuart
>
>From: Yuantian Tang <andy.t...@nxp.com>
>
>mux changes in board file to enable lpuart1 and macro define for lpuart1 used
>for mux changes in board configuation register 13
>
>Signed-off-by: Vabhav Sharma <vabhav.sha...@nxp.com>
>Signed-off-by: Yuantian Tang <andy.t...@nxp.com>
>---
> board/freescale/ls1028a/ls1028a.c | 32 +++++++++++++++++++++++++++++++
> include/configs/ls1028aqds.h | 7 +++++++
> 2 files changed, 39 insertions(+)
>
>diff --git a/board/freescale/ls1028a/ls1028a.c
>b/board/freescale/ls1028a/ls1028a.c
>index aa93534ac6..3659e7daf3 100644
>--- a/board/freescale/ls1028a/ls1028a.c
>+++ b/board/freescale/ls1028a/ls1028a.c
>@@ -31,6 +31,7 @@ DECLARE_GLOBAL_DATA_PTR;
>
> int config_board_mux(void)
> {
>+#ifndef CONFIG_LPUART
> #if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
> u8 reg;
>
>@@ -55,9 +56,18 @@ int config_board_mux(void)
> reg &= ~(0xc0);
> QIXIS_WRITE(brdcfg[15], reg);
> #endif
>+#endif
>+
> return 0;
> }
>
>+#ifdef CONFIG_LPUART
>+u32 get_lpuart_clk(void)
>+{
>+ return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV; } #endif
>+
> int board_init(void)
> {
> #ifdef CONFIG_ENV_IS_NOWHERE
>@@ -120,11 +130,33 @@ int misc_init_r(void)
>
> int board_early_init_f(void)
> {
>+#ifdef CONFIG_LPUART
>+ u8 uart;
>+#endif
>+
> #ifdef CONFIG_SYS_I2C_EARLY_INIT
> i2c_early_init_f();
> #endif
>
> fsl_lsch3_early_init_f();
>+
>+#ifdef CONFIG_LPUART
>+ /*
>+ * Field| Function
>+ * --------------------------------------------------------------
>+ * 7-6 | Controls I2C3 routing (net CFG_MUX_I2C3):
>+ * I2C3 | 11= Routes {SCL, SDA} to LPUART1 header as {SOUT, SIN}.
>+ * --------------------------------------------------------------
>+ * 5-4 | Controls I2C4 routing (net CFG_MUX_I2C4):
>+ * I2C4 |11= Routes {SCL, SDA} to LPUART1 header as {CTS_B, RTS_B}.
>+ */
>+ /* use lpuart0 as system console */
>+ uart = QIXIS_READ(brdcfg[13]);
>+ uart &= ~CFG_LPUART_MUX_MASK;
>+ uart |= CFG_LPUART_EN;
>+ QIXIS_WRITE(brdcfg[13], uart);
>+#endif
>+
> return 0;
> }
>
>diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h index
>982df07bb0..b3c12420eb 100644
>--- a/include/configs/ls1028aqds.h
>+++ b/include/configs/ls1028aqds.h
>@@ -66,6 +66,13 @@
> #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #endif
>
>+/* LPUART */
>+#ifdef CONFIG_LPUART
>+#define CONFIG_LPUART_32B_REG
>+#define CFG_LPUART_MUX_MASK 0xf0
>+#define CFG_LPUART_EN 0xf0
>+#endif
>+
> /* SATA */
> #define CONFIG_SCSI_AHCI_PLAT
>
>--
>2.17.1
Series applied on fsl-qoriq. Awaiting upstream.
In future, while sending v2 of series, please send the completes series again
if none of patch is merged yet. Its difficult to combine.
Thanks
Priyanka
