On Fri, 2020-04-24 at 18:50 +0200, Sylwester Nawrocki wrote: > From: Marek Szyprowski <m.szyprow...@samsung.com> > > Create a non-cacheable mapping for the 0x600000000 physical memory region, > where MMIO registers for the PCIe XHCI controller are instantiated by the > PCIe bridge. > > Signed-off-by: Marek Szyprowski <m.szyprow...@samsung.com> > --- > Changes since RFC: > - none.
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulie...@suse.de> Regards, Nicolas
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