> pllv3 PLLs have powerdown/up bits but enable bits too. Specifically > "enable bit" enable the pll output, so when dis/enabling pll by > setting/clearing power_bit we must also set/clear enable_bit. > Signed-off-by: Giulio Benetti <giulio.bene...@benettiengineering.com> > Reviewed-by: Lukasz Majewski <lu...@denx.de> Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =====================================================================
