SBI v0.2 is more scalable and extendable to handle future needs
for RISC-V supervisor interfaces. For example, with SBI v0.2 HSM
extension, only a single hart need to boot and enter operating
system. The booting hart can bring up secondary harts one by one
afterwards.
Signed-off-by: Bin Meng <bmeng...@gmail.com>
---
arch/riscv/Kconfig | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 502143f..ae801d3 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -226,14 +226,32 @@ config SBI
bool
default y if RISCV_SMODE || SPL_RISCV_SMODE
+choice
+ prompt "SBI support"
+ default SBI_V01
+
config SBI_V01
bool "SBI v0.1 support"
- default y
depends on SBI
help
This config allows kernel to use SBI v0.1 APIs. This will be
deprecated in future once legacy M-mode software are no longer in use.
+config SBI_V02
+ bool "SBI v0.2 support"
+ depends on SBI
+ help
+ This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
+ scalable and extendable to handle future needs for RISC-V supervisor
+ interfaces. For example, with SBI v0.2 HSM extension, only a single
+ hart need to boot and enter operating system. The booting hart can
+ bring up secondary harts one by one afterwards.
+
+ Choose this option if OpenSBI v0.7 or above release is used together
+ with U-Boot.
+
+endchoice
+
config SBI_IPI
bool
depends on SBI
--
2.7.4
