Hi, On 3/20/20 9:57 AM, Alex Nemirovsky wrote: > From: Arthur Li <arthur...@cortina-access.com> > > Initial DesignWare based DM support for Cortina Access CAxxxx SoCs. > > Signed-off-by: Arthur Li <arthur...@cortina-access.com> > Signed-off-by: Alex Nemirovsky <alex.nemirov...@cortina-access.com> > CC: Peng Fan <peng....@nxp.com>
I didn't receive any reply about my previous comments. And Is there patch v3 or v2? Subject is v2..but change log is v3. What is correct version? Best Regards, Jaehoon Chung > > --- > > Changes in v3: None > Changes in v2: > - Add I2C controller > - Add LED controller > - Add SPI NAND and NOR controller > > MAINTAINERS | 2 + > drivers/mmc/Kconfig | 11 +++ > drivers/mmc/Makefile | 1 + > drivers/mmc/ca_dw_mmc.c | 181 > ++++++++++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 195 insertions(+) > create mode 100644 drivers/mmc/ca_dw_mmc.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 82e4159..bb45d3c 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -180,6 +180,7 @@ F: board/cortina/common/ > F: drivers/gpio/cortina_gpio.c > F: drivers/watchdog/cortina_wdt.c > F: drivers/serial/serial_cortina.c > +F: drivers/mmc/ca_dw_mmc.c > > ARM/CZ.NIC TURRIS MOX SUPPORT > M: Marek Behun <marek.be...@nic.cz> > @@ -670,6 +671,7 @@ F: board/cortina/common/ > F: drivers/gpio/cortina_gpio.c > F: drivers/watchdog/cortina_wdt.c > F: drivers/serial/serial_cortina.c > +F: drivers/mmc/ca_dw_mmc.c > > MIPS MSCC > M: Gregory CLEMENT <gregory.clem...@bootlin.com> > diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig > index 2f0eedc..bb38787 100644 > --- a/drivers/mmc/Kconfig > +++ b/drivers/mmc/Kconfig > @@ -205,6 +205,17 @@ config MMC_DW > block, this provides host support for SD and MMC interfaces, in both > PIO, internal DMA mode and external DMA mode. > > +config MMC_DW_CORTINA > + bool "Cortina specific extensions for Synopsys DW Memory Card Interface" > + depends on DM_MMC > + depends on MMC_DW > + depends on BLK > + default n > + help > + This selects support for Cortina SoC specific extensions to the > + Synopsys DesignWare Memory Card Interface driver. Select this option > + for platforms based on Cortina CAxxxx Soc's. > + > config MMC_DW_EXYNOS > bool "Exynos specific extensions for Synopsys DW Memory Card Interface" > depends on ARCH_EXYNOS > diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile > index 9c1f8e5..615b724 100644 > --- a/drivers/mmc/Makefile > +++ b/drivers/mmc/Makefile > @@ -20,6 +20,7 @@ endif > obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o > obj-$(CONFIG_MMC_DAVINCI) += davinci_mmc.o > obj-$(CONFIG_MMC_DW) += dw_mmc.o > +obj-$(CONFIG_MMC_DW_CORTINA) += ca_dw_mmc.o > obj-$(CONFIG_MMC_DW_EXYNOS) += exynos_dw_mmc.o > obj-$(CONFIG_MMC_DW_K3) += hi6220_dw_mmc.o > obj-$(CONFIG_MMC_DW_ROCKCHIP) += rockchip_dw_mmc.o > diff --git a/drivers/mmc/ca_dw_mmc.c b/drivers/mmc/ca_dw_mmc.c > new file mode 100644 > index 0000000..acbc850 > --- /dev/null > +++ b/drivers/mmc/ca_dw_mmc.c > @@ -0,0 +1,181 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * (C) Copyright 2019 Cortina Access > + * Arthur Li <arthur...@cortina-access.com> > + */ > + > +#include <common.h> > +#include <dwmmc.h> > +#include <fdtdec.h> > +#include <linux/libfdt.h> > +#include <malloc.h> > +#include <errno.h> > +#include <dm.h> > +#include <mapmem.h> > + > +#define SD_CLK_SEL_MASK (0x3) > +#define SD_DLL_DEFAULT (0x143000) > +#define SD_SCLK_MAX (200000000) > + > +#define SD_CLK_SEL_200MHZ (0x2) > +#define SD_CLK_SEL_100MHZ (0x1) > + > +#define IO_DRV_SD_DS_OFFSET (16) > +#define IO_DRV_SD_DS_MASK (0xff << IO_DRV_SD_DS_OFFSET) > + > +#define MIN_FREQ (400000) > + > +DECLARE_GLOBAL_DATA_PTR; > + > +struct ca_mmc_plat { > + struct mmc_config cfg; > + struct mmc mmc; > +}; > + > +struct ca_dwmmc_priv_data { > + struct dwmci_host host; > + void __iomem *sd_dll_reg; > + void __iomem *io_drv_reg; > + u8 ds; > +}; > + > +static void ca_dwmci_clksel(struct dwmci_host *host) > +{ > + struct ca_dwmmc_priv_data *priv = host->priv; > + u32 val = readl(priv->sd_dll_reg); > + > + if (host->bus_hz >= 200000000) { > + val &= ~SD_CLK_SEL_MASK; > + val |= SD_CLK_SEL_200MHZ; > + } else if (host->bus_hz >= 100000000) { > + val &= ~SD_CLK_SEL_MASK; > + val |= SD_CLK_SEL_100MHZ; > + } else { > + val &= ~SD_CLK_SEL_MASK; > + } > + > + writel(val, priv->sd_dll_reg); > +} > + > +static void ca_dwmci_board_init(struct dwmci_host *host) > +{ > + struct ca_dwmmc_priv_data *priv = host->priv; > + u32 val = readl(priv->io_drv_reg); > + > + writel(SD_DLL_DEFAULT, priv->sd_dll_reg); > + > + val &= ~IO_DRV_SD_DS_MASK; > + if (priv && priv->ds) > + val |= priv->ds << IO_DRV_SD_DS_OFFSET; > + writel(val, priv->io_drv_reg); > +} > + > +unsigned int ca_dwmci_get_mmc_clock(struct dwmci_host *host, uint freq) > +{ > + struct ca_dwmmc_priv_data *priv = host->priv; > + u8 sd_clk_sel = readl(priv->sd_dll_reg) & SD_CLK_SEL_MASK; > + u8 clk_div; > + > + switch (sd_clk_sel) { > + case 2: > + clk_div = 1; > + break; > + case 1: > + clk_div = 2; > + break; > + default: > + clk_div = 4; > + } > + > + return SD_SCLK_MAX / clk_div / (host->div + 1); > +} > + > +static int ca_dwmmc_ofdata_to_platdata(struct udevice *dev) > +{ > + struct ca_dwmmc_priv_data *priv = dev_get_priv(dev); > + struct dwmci_host *host = &priv->host; > + u32 tmp; > + > + host->name = dev->name; > + host->dev_index = 0; > + > + host->buswidth = dev_read_u32_default(dev, "bus-width", 1); > + if (host->buswidth != 1 && host->buswidth != 4) > + return -EINVAL; > + > + host->bus_hz = dev_read_u32_default(dev, "max-frequency", 50000000); > + priv->ds = dev_read_u32_default(dev, "io_ds", 0x33); > + host->fifo_mode = dev_read_bool(dev, "fifo-mode"); > + > + dev_read_u32(dev, "sd_dll_ctrl", &tmp); > + priv->sd_dll_reg = map_sysmem((uintptr_t)tmp, sizeof(uintptr_t)); > + if (!priv->sd_dll_reg) > + return -EINVAL; > + > + dev_read_u32(dev, "io_drv_ctrl", &tmp); > + priv->io_drv_reg = map_sysmem((uintptr_t)tmp, sizeof(uintptr_t)); > + if (!priv->io_drv_reg) > + return -EINVAL; > + > + host->ioaddr = dev_read_addr_ptr(dev); > + if (host->ioaddr == (void *)FDT_ADDR_T_NONE) { > + printf("DWMMC: base address is invalid\n"); > + return -EINVAL; > + } > + > + host->priv = priv; > + > + return 0; > +} > + > +struct dm_mmc_ops ca_dwmci_dm_ops; > + > +static int ca_dwmmc_probe(struct udevice *dev) > +{ > + struct ca_mmc_plat *plat = dev_get_platdata(dev); > + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); > + struct ca_dwmmc_priv_data *priv = dev_get_priv(dev); > + struct dwmci_host *host = &priv->host; > + > + memcpy(&ca_dwmci_dm_ops, &dm_dwmci_ops, sizeof(struct dm_mmc_ops)); > + > + dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, MIN_FREQ); > + if (host->buswidth == 1) { > + (&plat->cfg)->host_caps &= ~MMC_MODE_8BIT; > + (&plat->cfg)->host_caps &= ~MMC_MODE_4BIT; > + } > + > + host->mmc = &plat->mmc; > + host->mmc->priv = &priv->host; > + upriv->mmc = host->mmc; > + host->mmc->dev = dev; > + host->clksel = ca_dwmci_clksel; > + host->board_init = ca_dwmci_board_init; > + host->get_mmc_clk = ca_dwmci_get_mmc_clock; > + > + return dwmci_probe(dev); > +} > + > +static int ca_dwmmc_bind(struct udevice *dev) > +{ > + struct ca_mmc_plat *plat = dev_get_platdata(dev); > + > + return dwmci_bind(dev, &plat->mmc, &plat->cfg); > +} > + > +static const struct udevice_id ca_dwmmc_ids[] = { > + { .compatible = "snps,dw-cortina" }, > + { } > +}; > + > +U_BOOT_DRIVER(ca_dwmmc_drv) = { > + .name = "cortina_dwmmc", > + .id = UCLASS_MMC, > + .of_match = ca_dwmmc_ids, > + .ofdata_to_platdata = ca_dwmmc_ofdata_to_platdata, > + .bind = ca_dwmmc_bind, > + .ops = &ca_dwmci_dm_ops, > + .probe = ca_dwmmc_probe, > + .priv_auto_alloc_size = sizeof(struct ca_dwmmc_priv_data), > + .platdata_auto_alloc_size = sizeof(struct ca_mmc_plat), > +}; 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