[PATCH 3/9] armv8: dts: ls1046a: Add the PCIe EP node

[Xiaowei Bao]

Add the PCIe EP node for ls1046a.

Signed-off-by: Xiaowei Bao <xiaowei....@nxp.com>
---
 arch/arm/dts/fsl-ls1046a.dtsi | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index fdf93fd..e4b4a8e 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -259,6 +259,17 @@
                                  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 
0x40000000>; /* non-prefetchable memory */
                };
 
+               pcie_ep@3400000 {
+                       compatible = "fsl,ls-pcie-ep";
+                       reg = <0x00 0x03400000 0x0 0x80000
+                              0x00 0x034c0000 0x0 0x40000
+                              0x40 0x00000000 0x8 0x00000000>;
+                       reg-names = "regs", "ctrl", "addr_space";
+                       num-ib-windows = <6>;
+                       num-ob-windows = <8>;
+                       big-endian;
+               };
+
                pcie@3500000 {
                        compatible = "fsl,ls-pcie", "snps,dw-pcie";
                        reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
@@ -276,6 +287,17 @@
                                  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 
0x40000000>; /* non-prefetchable memory */
                };
 
+               pcie_ep@3500000 {
+                       compatible = "fsl,ls-pcie-ep";
+                       reg = <0x00 0x03500000 0x0 0x80000
+                              0x00 0x035c0000 0x0 0x40000
+                              0x48 0x00000000 0x8 0x00000000>;
+                       reg-names = "regs", "ctrl", "addr_space";
+                       num-ib-windows = <6>;
+                       num-ob-windows = <8>;
+                       big-endian;
+               };
+
                pcie@3600000 {
                        compatible = "fsl,ls-pcie", "snps,dw-pcie";
                        reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
@@ -292,6 +314,17 @@
                                  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 
0x40000000>; /* non-prefetchable memory */
                };
 
+               pcie_ep@3600000 {
+                       compatible = "fsl,ls-pcie-ep";
+                       reg = <0x00 0x03600000 0x0 0x80000
+                              0x00 0x036c0000 0x0 0x40000
+                              0x50 0x00000000 0x8 0x00000000>;
+                       reg-names = "regs", "ctrl", "addr_space";
+                       num-ib-windows = <6>;
+                       num-ob-windows = <8>;
+                       big-endian;
+               };
+
                sata: sata@3200000 {
                        compatible = "fsl,ls1046a-ahci";
                        reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
-- 
2.9.5