Hi Chris, On Wed, Feb 26 2020, Chris Packham wrote: > From: Chris Packham <chris.pack...@alliedtelesis.co.nz> > > Update the RTC (Read Timing Control) values for PCIe memory wrappers > following an ERRATA (ERRATA# TDB). This means the PCIe accesses will > used slower memory Read Timing, to allow more efficient energy > consumption, in order to lower the minimum VDD of the memory. Will lead > to more robust memory when voltage drop occurs (VDDSEG)
Have you seen memory access reliability problems because of this issue? > The code is based on changes from Marvell's U-Boot, specifically: > > https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b > https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 > https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b > https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b The last link looks duplicated. baruch -- http://baruch.siach.name/blog/ ~. .~ Tk Open Systems =}------------------------------------------------ooO--U--Ooo------------{= - bar...@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
