On Tue, Jan 28, 2020 at 3:43 PM Marcel Ziswiler <mar...@ziswiler.com> wrote: > > From: Marcel Ziswiler <marcel.ziswi...@toradex.com> > > Synchronise with latest linux-next kernel pin func header file. > > Signed-off-by: Marcel Ziswiler <marcel.ziswi...@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvo...@toradex.com> > > --- > > Changes in v3: > - Drop pinfunc patches and just sync with linux-next as suggested by > Fabio, Frieder and Oleksandr. > > Changes in v2: None > > arch/arm/dts/imx8mm-pinfunc.h | 20 ++++++++++++++++++-- > 1 file changed, 18 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/dts/imx8mm-pinfunc.h b/arch/arm/dts/imx8mm-pinfunc.h > index e25f7fcd79..5ccc4cc919 100644 > --- a/arch/arm/dts/imx8mm-pinfunc.h > +++ b/arch/arm/dts/imx8mm-pinfunc.h > @@ -430,18 +430,26 @@ > #define MX8MM_IOMUXC_SAI1_MCLK_SIM_M_HRESP > 0x1AC 0x414 0x000 0x7 0x0 > #define MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC > 0x1B0 0x418 0x000 0x0 0x0 > #define MX8MM_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC > 0x1B0 0x418 0x4EC 0x1 0x2 > +#define MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX > 0x1B0 0x418 0x000 0x4 0x0 > +#define MX8MM_IOMUXC_SAI2_RXFS_UART1_DTE_RX > 0x1B0 0x418 0x4F4 0x4 0x2 > #define MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 > 0x1B0 0x418 0x000 0x5 0x0 > #define MX8MM_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 > 0x1B0 0x418 0x000 0x7 0x0 > #define MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK > 0x1B4 0x41C 0x000 0x0 0x0 > #define MX8MM_IOMUXC_SAI2_RXC_SAI5_TX_BCLK > 0x1B4 0x41C 0x4E8 0x1 0x2 > +#define MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX > 0x1B4 0x41C 0x4F4 0x4 0x3 > +#define MX8MM_IOMUXC_SAI2_RXC_UART1_DTE_TX > 0x1B4 0x41C 0x000 0x4 0x0 > #define MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 > 0x1B4 0x41C 0x000 0x5 0x0 > #define MX8MM_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 > 0x1B4 0x41C 0x000 0x7 0x0 > #define MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 > 0x1B8 0x420 0x000 0x0 0x0 > #define MX8MM_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 > 0x1B8 0x420 0x000 0x1 0x0 > +#define MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B > 0x1B8 0x420 0x4F0 0x4 0x2 > +#define MX8MM_IOMUXC_SAI2_RXD0_UART1_DTE_CTS_B > 0x1B8 0x420 0x000 0x4 0x0 > #define MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 > 0x1B8 0x420 0x000 0x5 0x0 > #define MX8MM_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 > 0x1B8 0x420 0x000 0x7 0x0 > #define MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC > 0x1BC 0x424 0x000 0x0 0x0 > #define MX8MM_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 > 0x1BC 0x424 0x000 0x1 0x0 > +#define MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B > 0x1BC 0x424 0x000 0x4 0x0 > +#define MX8MM_IOMUXC_SAI2_TXFS_UART1_DTE_RTS_B > 0x1BC 0x424 0x4F0 0x4 0x3 > #define MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 > 0x1BC 0x424 0x000 0x5 0x0 > #define MX8MM_IOMUXC_SAI2_TXFS_SIM_M_HWRITE > 0x1BC 0x424 0x000 0x7 0x0 > #define MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK > 0x1C0 0x428 0x000 0x0 0x0 > @@ -462,23 +470,31 @@ > #define MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 > 0x1CC 0x434 0x000 0x5 0x0 > #define MX8MM_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 > 0x1CC 0x434 0x000 0x7 0x0 > #define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK > 0x1D0 0x438 0x000 0x0 0x0 > -#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 > 0x1D0 0x438 0x000 0x1 0x0 > +#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CLK > 0x1D0 0x438 0x000 0x1 0x0 > #define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK > 0x1D0 0x438 0x4D0 0x2 0x2 > +#define MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B > 0x1D0 0x438 0x000 0x4 0x0 > +#define MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B > 0x1D0 0x438 0x4F8 0x4 0x2 > #define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 > 0x1D0 0x438 0x000 0x5 0x0 > #define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 > 0x1D0 0x438 0x000 0x7 0x0 > #define MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 > 0x1D4 0x43C 0x000 0x0 0x0 > #define MX8MM_IOMUXC_SAI3_RXD_GPT1_COMPARE1 > 0x1D4 0x43C 0x000 0x1 0x0 > #define MX8MM_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 > 0x1D4 0x43C 0x4D4 0x2 0x2 > +#define MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B > 0x1D4 0x43C 0x4F8 0x4 0x3 > +#define MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B > 0x1D4 0x43C 0x000 0x4 0x0 > #define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 > 0x1D4 0x43C 0x000 0x5 0x0 > #define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0 > 0x1D4 0x43C 0x000 0x7 0x0 > #define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC > 0x1D8 0x440 0x000 0x0 0x0 > -#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CLK > 0x1D8 0x440 0x000 0x1 0x0 > +#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 > 0x1D8 0x440 0x000 0x1 0x0 > #define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 > 0x1D8 0x440 0x4D8 0x2 0x2 > +#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX > 0x1D8 0x440 0x4Fc 0x4 0x2 > +#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX > 0x1D8 0x440 0x000 0x4 0x0 > #define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 > 0x1D8 0x440 0x000 0x5 0x0 > #define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 > 0x1D8 0x440 0x000 0x7 0x0 > #define MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK > 0x1DC 0x444 0x000 0x0 0x0 > #define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2 > 0x1DC 0x444 0x000 0x1 0x0 > #define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 > 0x1DC 0x444 0x4DC 0x2 0x2 > +#define MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX > 0x1DC 0x444 0x000 0x4 0x0 > +#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX > 0x1DC 0x444 0x4Fc 0x4 0x3 > #define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 > 0x1DC 0x444 0x000 0x5 0x0 > #define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2 > 0x1DC 0x444 0x000 0x7 0x0 > #define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 > 0x1E0 0x448 0x000 0x0 0x0 > -- > 2.24.1 > -- Best regards Oleksandr Suvorov cryo...@gmail.com
