>There is nothing to 'implement'. Page mode flash has a >timing parameter indicating the time to the first read, >and then the time for subsequent reads within a page >to return. > >If you are interfacing to this flash using a processor >local bus controller, then you generally only have one >read timing parameter you can configure. In that case, >you would have to configure the local bus controller >read timing of the processor to the flash worst-case >value, i.e., the timing for the read of the first word >in a page.
The local bus controller of your processor have to support the page mode for NOR Flash. IIRC, The GPCM of PQx doesn't support such feature right now. >If you are interfacing to the flash using an FPGA, then >you can exploit this feature. For example, I use this >feature to get optimal read timing from a FPGA configuration >controller. It is easy to control the timing for FPGA. Thanks, Dave _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
