Hi, I'm working on a custom board based on FSL P1011. The board has 128MB of soldered DDR2 connected to a single chip select. Simulation results indicate that better DDR2 behavior would be achieved by using half strength DDR drivers. The driver strength on P1011 is controlled by DDR_SDRAM_CFG[HSE] and various fields in DDR_CDR_1. I also need to configure DDR ODT, which is controlled by DDR_CDR_2 register.
The problem is that DDR setup code for P1020/P1011 does not configure DDR_CDR_X registers. I was tempted to add them to struct fsl_ddr_cfg_regs_s, and modify fsl_ddr_set_memctl_regs() in ddr_gen2.c to deal with them, but noticed that on some 85XX SoC (e.g. MPC8548), there's a single DDR_CDR register, which is not part of DDR CCSR space. Which means that current definition of struct ccsr_ddr in immap_85xx.h is not correct for these SoCs. How would you suggest to solve my problem in a generic way ? Thanks. Felix. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
