Function sscg_pll_init() is not used anywhere, so it can simply be deleted.
This was found because of the following sparse
warning:
arch/arm/mach-imx/imx8m/clock_imx8mq.c:702:5: warning: no previous prototype
for ???sscg_pll_init??? [-Wmissing-prototypes]
int sscg_pll_init(u32 pll)
^~~~~~~~~~~~~
Signed-off-by: Pedro Jardim <jardim.c.pe...@gmail.com>
---
Chages since v1:
- Fixed patch corruption
arch/arm/mach-imx/imx8m/clock_imx8mq.c | 71 --------------------------
1 file changed, 71 deletions(-)
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c
b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
index d8530cc808..72a70d8c45 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
@@ -677,77 +677,6 @@ int frac_pll_init(u32 pll, enum frac_pll_out_val val)
return 0;
}
-int sscg_pll_init(u32 pll)
-{
- void __iomem *pll_cfg0, __iomem *pll_cfg1, __iomem *pll_cfg2;
- u32 val_cfg0, val_cfg1, val_cfg2, val;
- u32 bypass1_mask = 0x20, bypass2_mask = 0x10;
- int ret;
-
- switch (pll) {
- case ANATOP_SYSTEM_PLL1:
- pll_cfg0 = &ana_pll->sys_pll1_cfg0;
- pll_cfg1 = &ana_pll->sys_pll1_cfg1;
- pll_cfg2 = &ana_pll->sys_pll1_cfg2;
- /* 800MHz */
- val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
- SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
- val_cfg1 = 0;
- val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
- SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
- SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
- SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
- SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
- SSCG_PLL_REFCLK_SEL_OSC_25M;
- break;
- case ANATOP_SYSTEM_PLL2:
- pll_cfg0 = &ana_pll->sys_pll2_cfg0;
- pll_cfg1 = &ana_pll->sys_pll2_cfg1;
- pll_cfg2 = &ana_pll->sys_pll2_cfg2;
- /* 1000MHz */
- val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
- SSCG_PLL_FEEDBACK_DIV_F2_VAL(4);
- val_cfg1 = 0;
- val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
- SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
- SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
- SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
- SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
- SSCG_PLL_REFCLK_SEL_OSC_25M;
- break;
- case ANATOP_SYSTEM_PLL3:
- pll_cfg0 = &ana_pll->sys_pll3_cfg0;
- pll_cfg1 = &ana_pll->sys_pll3_cfg1;
- pll_cfg2 = &ana_pll->sys_pll3_cfg2;
- /* 800MHz */
- val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
- SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
- val_cfg1 = 0;
- val_cfg0 = SSCG_PLL_PLL3_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
- SSCG_PLL_REFCLK_SEL_OSC_25M;
- break;
- default:
- return -EINVAL;
- }
-
- /*bypass*/
- setbits_le32(pll_cfg0, bypass1_mask | bypass2_mask);
- /* set value */
- writel(val_cfg2, pll_cfg2);
- writel(val_cfg1, pll_cfg1);
- /*unbypass1 and wait 70us */
- writel(val_cfg0 | bypass2_mask, pll_cfg1);
-
- __udelay(70);
-
- /* unbypass2 and wait lock */
- writel(val_cfg0, pll_cfg1);
- ret = readl_poll_timeout(pll_cfg0, val, val & SSCG_PLL_LOCK_MASK, 1);
- if (ret)
- printf("%s timeout\n", __func__);
-
- return ret;
-}
int clock_init(void)
{
--
2.17.1
