Hi Anup,
>-----Original Message-----
>From: Anup Patel <a...@brainfault.org>
>Sent: 20 January 2020 10:26
>To: Pragnesh Patel <pragnesh.pa...@sifive.com>
>Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Palmer Dabbelt
><palmerdabb...@google.com>; Atish Patra <atish.pa...@wdc.com>
>Subject: Re: [PATCH v2 3/9] Sifive: FU540: Add header files for SoC
>
>On Fri, Jan 17, 2020 at 6:17 PM Pragnesh Patel <pragnesh.pa...@sifive.com>
>wrote:
>>
>> Add fu540 SoC specific header files
>>
>> Signed-off-by: Pragnesh Patel <pragnesh.pa...@sifive.com>
>> ---
>> arch/riscv/include/asm/arch-fu540/cache.h | 42 ++++++++++
>> arch/riscv/include/asm/arch-fu540/gpio.h | 14 ++++
>> arch/riscv/include/asm/arch-fu540/otp.h | 80 +++++++++++++++++++
>> arch/riscv/include/asm/arch-fu540/spi.h | 15 ++++
>> arch/riscv/include/asm/arch-fu540/uart.h | 14 ++++
>> arch/riscv/include/asm/arch-generic/gpio.h | 32 +-------
>> arch/riscv/include/asm/arch-sifive/gpio.h | 42 ++++++++++
>> arch/riscv/include/asm/arch-sifive/spi.h | 93 ++++++++++++++++++++++
>> arch/riscv/include/asm/arch-sifive/uart.h | 35 ++++++++
>> drivers/spi/spi-sifive.c | 81 +------------------
>> 10 files changed, 339 insertions(+), 109 deletions(-) create mode
>> 100644 arch/riscv/include/asm/arch-fu540/cache.h
>> create mode 100644 arch/riscv/include/asm/arch-fu540/gpio.h
>> create mode 100644 arch/riscv/include/asm/arch-fu540/otp.h
>> create mode 100644 arch/riscv/include/asm/arch-fu540/spi.h
>> create mode 100644 arch/riscv/include/asm/arch-fu540/uart.h
>> create mode 100644 arch/riscv/include/asm/arch-sifive/gpio.h
>> create mode 100644 arch/riscv/include/asm/arch-sifive/spi.h
>> create mode 100644 arch/riscv/include/asm/arch-sifive/uart.h
>>
>> diff --git a/arch/riscv/include/asm/arch-fu540/cache.h
>> b/arch/riscv/include/asm/arch-fu540/cache.h
>> new file mode 100644
>> index 0000000000..e84d56774c
>> --- /dev/null
>> +++ b/arch/riscv/include/asm/arch-fu540/cache.h
>> @@ -0,0 +1,42 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright (C) 2019 SiFive, Inc.
>> + *
>> + * Authors:
>> + * Pragnesh Patel <pragnesh.pa...@sifive.com>
>> + */
>> +
>> +#ifndef _CACHE_FU540_H
>> +#define _CACHE_FU540_H
>> +
>> +/* Register offsets */
>> +#define CCACHE_INFO 0x000
>> +#define CCACHE_ENABLE 0x008
>> +#define CCACHE_INJECT 0x040
>> +#define CCACHE_META_FIX 0x100
>> +#define CCACHE_DATA_FIX 0x140
>> +#define CCACHE_DATA_FAIL 0x160
>> +#define CCACHE_FLUSH64 0x200
>> +#define CCACHE_FLUSH32 0x240
>> +#define CCACHE_WAYS 0x800
>> +
>> +/* Bytes inside the INFO field */
>> +#define CCACHE_INFO_BANKS 0
>> +#define CCACHE_INFO_WAYS 1
>> +#define CCACHE_INFO_LG_SETS 2
>> +#define CCACHE_INFO_LG_BLOCKBYTES 3
>> +
>> +/* INJECT types */
>> +#define CCACHE_ECC_TOGGLE_DATA 0x00000 #define
>> +CCACHE_ECC_TOGGLE_META 0x10000
>> +
>> +/* Offsets per FIX/FAIL */
>> +#define CCACHE_ECC_ADDR 0x0
>> +#define CCACHE_ECC_COUNT 0x8
>> +
>> +/* Interrupt Number offsets from Base */
>> +#define CCACHE_INT_META_FIX 0
>> +#define CCACHE_INT_DATA_FIX 1
>> +#define CCACHE_INT_DATA_FAIL 2
>> +
>> +#endif /* _CACHE_FU540_H */
>> diff --git a/arch/riscv/include/asm/arch-fu540/gpio.h
>> b/arch/riscv/include/asm/arch-fu540/gpio.h
>> new file mode 100644
>> index 0000000000..8210ff8551
>> --- /dev/null
>> +++ b/arch/riscv/include/asm/arch-fu540/gpio.h
>> @@ -0,0 +1,14 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright (C) 2019 SiFive, Inc.
>> + *
>> + * Authors:
>> + * Pragnesh Patel <pragnesh.pa...@sifive.com>
>> + */
>> +
>> +#ifndef _GPIO_FU540_H
>> +#define _GPIO_FU540_H
>> +
>> +#include <asm/arch-sifive/gpio.h>
>> +
>> +#endif /* _GPIO_FU540_H */
>> diff --git a/arch/riscv/include/asm/arch-fu540/otp.h
>> b/arch/riscv/include/asm/arch-fu540/otp.h
>> new file mode 100644
>> index 0000000000..a498593d39
>> --- /dev/null
>> +++ b/arch/riscv/include/asm/arch-fu540/otp.h
>> @@ -0,0 +1,80 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright (C) 2019 SiFive, Inc.
>> + *
>> + * Authors:
>> + * Pragnesh Patel <pragnesh.pa...@sifive.com>
>> + * Troy Benjegerdes <troy.benjeger...@sifive.com>
>> + */
>> +
>> +#ifndef _OTP_FU540_H
>> +#define _OTP_FU540_H
>> +
>> +/* Register offsets */
>> +#define EMEMORYOTP_PA 0x00
>> +#define EMEMORYOTP_PAIO 0x04
>> +#define EMEMORYOTP_PAS 0x08
>> +#define EMEMORYOTP_PCE 0x0C
>> +#define EMEMORYOTP_PCLK 0x10
>> +#define EMEMORYOTP_PDIN 0x14
>> +#define EMEMORYOTP_PDOUT 0x18
>> +#define EMEMORYOTP_PDSTB 0x1C
>> +#define EMEMORYOTP_PPROG 0x20
>> +#define EMEMORYOTP_PTC 0x24
>> +#define EMEMORYOTP_PTM 0x28
>> +#define EMEMORYOTP_PTM_REP 0x2C
>> +#define EMEMORYOTP_PTR 0x30
>> +#define EMEMORYOTP_PTRIM 0x34
>> +#define EMEMORYOTP_PWE 0x38
>> +
>> +/* Timing delays (in us)
>> + * MIN indicates that there is no maximum.
>> + * TYP indicates that there is a maximum
>> + * that should not be exceeded.
>> + * When the minimums are < 1us, I just put 1us.
>> + */
>> +
>> +#define EMEMORYOTP_MIN_TVDS 1
>> +#define EMEMORYOTP_MIN_TSAS 2
>> +#define EMEMORYOTP_MIN_TTAS 50
>> +#define EMEMORYOTP_MIN_TTAH 1
>> +#define EMEMORYOTP_MIN_TASH 1
>> +#define EMEMORYOTP_MIN_TMS 1
>> +#define EMEMORYOTP_MIN_TCS 10
>> +#define EMEMORYOTP_MIN_TMH 1
>> +#define EMEMORYOTP_MIN_TAS 50
>> +
>> +#define EMEMORYOTP_MAX_TCD 1
>> +#define EMEMORYOTP_MIN_TKH 1
>> +
>> +/* Note: This has an upper limit of 100 */
>> +#define EMEMORYOTP_MIN_TCSP 10
>> +#define EMEMORYOTP_TYP_TCSP 11
>> +
>> +/* This has an upper limit of 20 */
>> +#define EMEMORYOTP_MIN_TPPS 5
>> +#define EMEMORYOTP_TYP_TPPS 6
>> +
>> +/* This has an upper limit of 20 */
>> +#define EMEMORYOTP_MIN_TPPH 1
>> +#define EMEMORYOTP_TYP_TPPH 2
>> +
>> +/* This has upper limit of 100 */
>> +#define EMEMORYOTP_MIN_TPPR 5
>> +#define EMEMORYOTP_TYP_TPPR 6
>> +
>> +/* This has upper limit of 20 */
>> +#define EMEMORYOTP_MIN_TPW 10
>> +#define EMEMORYOTP_TYP_TPW 11
>> +
>> +#define EMEMORYOTP_MIN_TASP 1
>> +#define EMEMORYOTP_MIN_TDSP 1
>> +
>> +#define EMEMORYOTP_MIN_TAHP 1
>> +#define EMEMORYOTP_MIN_TDHP 1
>> +
>> +/* This has a max of 5! */
>> +#define EMEMORYOTP_MIN_TPWI 1
>> +#define EMEMORYOTP_TYP_TPWI 2
>> +
>> +#endif /* _OTP_FU540_H */
>> diff --git a/arch/riscv/include/asm/arch-fu540/spi.h
>> b/arch/riscv/include/asm/arch-fu540/spi.h
>> new file mode 100644
>> index 0000000000..c3a4a65efe
>> --- /dev/null
>> +++ b/arch/riscv/include/asm/arch-fu540/spi.h
>> @@ -0,0 +1,15 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright (C) 2019 SiFive, Inc.
>> + *
>> + * Authors:
>> + * Pragnesh Patel <pragnesh.pa...@sifive.com>
>> + * Troy Benjegerdes <troy.benjeger...@sifive.com>
>> + */
>> +
>> +#ifndef _SPI_FU540_H
>> +#define _SPI_FU540_H
>> +
>> +#include <asm/arch-sifive/spi.h>
>> +
>> +#endif /* _SPI_FU540_H */
>> diff --git a/arch/riscv/include/asm/arch-fu540/uart.h
>> b/arch/riscv/include/asm/arch-fu540/uart.h
>> new file mode 100644
>> index 0000000000..ca57a48588
>> --- /dev/null
>> +++ b/arch/riscv/include/asm/arch-fu540/uart.h
>> @@ -0,0 +1,14 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright (C) 2019 SiFive, Inc.
>> + *
>> + * Authors:
>> + * Pragnesh Patel <pragnesh.pa...@sifive.com>
>> + */
>> +
>> +#ifndef _UART_FU540_H
>> +#define _UART_FU540_H
>> +
>> +#include <asm/arch-sifive/uart.h>
>> +
>> +#endif /* _UART_FU540_H */
>> diff --git a/arch/riscv/include/asm/arch-generic/gpio.h
>> b/arch/riscv/include/asm/arch-generic/gpio.h
>> index dfcb753051..5f0dc0a801 100644
>> --- a/arch/riscv/include/asm/arch-generic/gpio.h
>> +++ b/arch/riscv/include/asm/arch-generic/gpio.h
>> @@ -3,33 +3,7 @@
>> * Copyright (C) 2019 SiFive, Inc.
>> */
>>
>> -#ifndef _GPIO_SIFIVE_H
>> -#define _GPIO_SIFIVE_H
>> +#ifndef __ASM_RISCV_ARCH_GPIO_H
>> +#define __ASM_RISCV_ARCH_GPIO_H
>>
>> -#define GPIO_INPUT_VAL 0x00
>> -#define GPIO_INPUT_EN 0x04
>> -#define GPIO_OUTPUT_EN 0x08
>> -#define GPIO_OUTPUT_VAL 0x0C
>> -#define GPIO_RISE_IE 0x18
>> -#define GPIO_RISE_IP 0x1C
>> -#define GPIO_FALL_IE 0x20
>> -#define GPIO_FALL_IP 0x24
>> -#define GPIO_HIGH_IE 0x28
>> -#define GPIO_HIGH_IP 0x2C
>> -#define GPIO_LOW_IE 0x30
>> -#define GPIO_LOW_IP 0x34
>> -#define GPIO_OUTPUT_XOR 0x40
>> -
>> -#define NR_GPIOS 16
>> -
>> -enum gpio_state {
>> - LOW,
>> - HIGH
>> -};
>> -
>> -/* Details about a GPIO bank */
>> -struct sifive_gpio_platdata {
>> - void *base; /* address of registers in physical memory */
>> -};
>> -
>> -#endif /* _GPIO_SIFIVE_H */
>> +#endif /* __ASM_RISCV_ARCH_GPIO_H */
>> diff --git a/arch/riscv/include/asm/arch-sifive/gpio.h
>> b/arch/riscv/include/asm/arch-sifive/gpio.h
>> new file mode 100644
>> index 0000000000..b6d56ee83c
>> --- /dev/null
>> +++ b/arch/riscv/include/asm/arch-sifive/gpio.h
>> @@ -0,0 +1,42 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright (C) 2019 SiFive, Inc.
>> + *
>> + * Authors:
>> + * Sagar Shrikant Kadam <sagar.ka...@sifive.com>
>> + */
>> +
>> +#ifndef _GPIO_SIFIVE_H
>> +#define _GPIO_SIFIVE_H
>> +
>> +#define GPIO_INPUT_VAL (0x00)
>> +#define GPIO_INPUT_EN (0x04)
>> +#define GPIO_OUTPUT_EN (0x08)
>> +#define GPIO_OUTPUT_VAL (0x0C)
>> +#define GPIO_PULLUP_EN (0x10)
>> +#define GPIO_DRIVE (0x14)
>> +#define GPIO_RISE_IE (0x18)
>> +#define GPIO_RISE_IP (0x1C)
>> +#define GPIO_FALL_IE (0x20)
>> +#define GPIO_FALL_IP (0x24)
>> +#define GPIO_HIGH_IE (0x28)
>> +#define GPIO_HIGH_IP (0x2C)
>> +#define GPIO_LOW_IE (0x30)
>> +#define GPIO_LOW_IP (0x34)
>> +#define GPIO_IOF_EN (0x38)
>> +#define GPIO_IOF_SEL (0x3C)
>> +#define GPIO_OUTPUT_XOR (0x40)
>> +
>> +#define NR_GPIOS 16
>> +
>> +enum gpio_state {
>> + LOW,
>> + HIGH
>> +};
>> +
>> +/* Details about a GPIO bank */
>> +struct sifive_gpio_platdata {
>> + void *base; /* address of registers in physical memory */
>> +};
>> +
>> +#endif /* _GPIO_SIFIVE_H */
>> diff --git a/arch/riscv/include/asm/arch-sifive/spi.h
>> b/arch/riscv/include/asm/arch-sifive/spi.h
>> new file mode 100644
>> index 0000000000..5f418849c5
>> --- /dev/null
>> +++ b/arch/riscv/include/asm/arch-sifive/spi.h
>> @@ -0,0 +1,93 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright (C) 2019 SiFive, Inc.
>> + *
>> + * Authors:
>> + * Pragnesh Patel <pragnesh.pa...@sifive.com>
>> + * Troy Benjegerdes <troy.benjeger...@sifive.com>
>> + */
>> +
>> +#ifndef _SPI_SIFIVE_H
>> +#define _SPI_SIFIVE_H
>> +
>> +/* register offsets */
>> +#define SIFIVE_SPI_REG_SCKDIV 0x00 /* Serial clock divisor */
>> +#define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */
>> +#define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */
>> +#define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */
>> +#define SIFIVE_SPI_REG_CSMODE 0x18 /* Chip select mode */
>> +#define SIFIVE_SPI_REG_DELAY0 0x28 /* Delay control 0 */
>> +#define SIFIVE_SPI_REG_DELAY1 0x2c /* Delay control 1 */
>> +#define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */
>> +#define SIFIVE_SPI_REG_TXDATA 0x48 /* Tx FIFO data */
>> +#define SIFIVE_SPI_REG_RXDATA 0x4c /* Rx FIFO data */
>> +#define SIFIVE_SPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
>> +#define SIFIVE_SPI_REG_RXMARK 0x54 /* Rx FIFO watermark */
>> +#define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface
>> control */
>> +#define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction
>> format
>*/
>> +#define SIFIVE_SPI_REG_IE 0x70 /* Interrupt Enable Register
>> */
>> +#define SIFIVE_SPI_REG_IP 0x74 /* Interrupt Pendings
>> Register */
>> +
>> +/* sckdiv bits */
>> +#define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU
>> +
>> +/* sckmode bits */
>> +#define SIFIVE_SPI_SCKMODE_PHA BIT(0)
>> +#define SIFIVE_SPI_SCKMODE_POL BIT(1)
>> +#define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA
>| \
>> + SIFIVE_SPI_SCKMODE_POL)
>> +
>> +/* csmode bits */
>> +#define SIFIVE_SPI_CSMODE_MODE_AUTO 0U
>> +#define SIFIVE_SPI_CSMODE_MODE_HOLD 2U
>> +#define SIFIVE_SPI_CSMODE_MODE_OFF 3U
>> +
>> +/* delay0 bits */
>> +#define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x))
>> +#define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU
>> +#define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16)
>> +#define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16)
>> +
>> +/* delay1 bits */
>> +#define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x))
>> +#define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU
>> +#define SIFIVE_SPI_DELAY1_INTERXFR(x) ((u32)(x) << 16)
>> +#define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16)
>> +
>> +/* fmt bits */
>> +#define SIFIVE_SPI_FMT_PROTO_SINGLE 0U
>> +#define SIFIVE_SPI_FMT_PROTO_DUAL 1U
>> +#define SIFIVE_SPI_FMT_PROTO_QUAD 2U
>> +#define SIFIVE_SPI_FMT_PROTO_MASK 3U
>> +#define SIFIVE_SPI_FMT_ENDIAN BIT(2)
>> +#define SIFIVE_SPI_FMT_DIR BIT(3)
>> +#define SIFIVE_SPI_FMT_LEN(x) ((u32)(x) << 16)
>> +#define SIFIVE_SPI_FMT_LEN_MASK (0xfU << 16)
>> +
>> +/* txdata bits */
>> +#define SIFIVE_SPI_TXDATA_DATA_MASK 0xffU
>> +#define SIFIVE_SPI_TXDATA_FULL BIT(31)
>> +
>> +/* rxdata bits */
>> +#define SIFIVE_SPI_RXDATA_DATA_MASK 0xffU
>> +#define SIFIVE_SPI_RXDATA_EMPTY BIT(31)
>> +
>> +/* ie and ip bits */
>> +#define SIFIVE_SPI_IP_TXWM BIT(0)
>> +#define SIFIVE_SPI_IP_RXWM BIT(1)
>> +
>> +struct sifive_spi {
>> + void *regs; /* base address of the registers */
>> + u32 fifo_depth;
>> + u32 bits_per_word;
>> + u32 cs_inactive; /* Level of the CS pins when
>> inactive*/
>> + u32 freq;
>> + u32 num_cs;
>> +};
>> +
>> +#define SIFIVE_SPI_MAX_CS 32
>> +
>> +#define SIFIVE_SPI_DEFAULT_DEPTH 8
>> +#define SIFIVE_SPI_DEFAULT_BITS 8
>> +
>> +#endif /* _SPI_SIFIVE_H */
>> diff --git a/arch/riscv/include/asm/arch-sifive/uart.h
>> b/arch/riscv/include/asm/arch-sifive/uart.h
>> new file mode 100644
>> index 0000000000..c9c7b104a6
>> --- /dev/null
>> +++ b/arch/riscv/include/asm/arch-sifive/uart.h
>> @@ -0,0 +1,35 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright (C) 2019 SiFive, Inc.
>> + *
>> + * Authors:
>> + * Pragnesh Patel <pragnesh.pa...@sifive.com>
>> + * Troy Benjegerdes <troy.benjeger...@sifive.com>
>> + */
>> +
>> +#ifndef _UART_SIFIVE_H
>> +#define _UART_SIFIVE_H
>> +
>> +/* Register offsets */
>> +#define UART_REG_TXFIFO 0x00
>> +#define UART_REG_RXFIFO 0x04
>> +#define UART_REG_TXCTRL 0x08
>> +#define UART_REG_RXCTRL 0x0c
>> +#define UART_REG_IE 0x10
>> +#define UART_REG_IP 0x14
>> +#define UART_REG_DIV 0x18
>> +
>> +/* TXCTRL register */
>> +#define UART_TXEN 0x1
>> +#define UART_TXNSTOP 0x2
>> +#define UART_TXWM(x) (((x) & 0xffff) << 16)
>> +
>> +/* RXCTRL register */
>> +#define UART_RXEN 0x1
>> +#define UART_RXWM(x) (((x) & 0xffff) << 16)
>> +
>> +/* IP register */
>> +#define UART_IP_TXWM 0x1
>> +#define UART_IP_RXWM 0x2
>> +
>> +#endif /* _UART_SIFIVE_H */
>> diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c index
>> 969bd4b75c..4a3cc49aa3 100644
>> --- a/drivers/spi/spi-sifive.c
>> +++ b/drivers/spi/spi-sifive.c
>> @@ -13,86 +13,7 @@
>> #include <asm/io.h>
>> #include <linux/log2.h>
>> #include <clk.h>
>> -
>> -#define SIFIVE_SPI_MAX_CS 32
>> -
>> -#define SIFIVE_SPI_DEFAULT_DEPTH 8
>> -#define SIFIVE_SPI_DEFAULT_BITS 8
>> -
>> -/* register offsets */
>> -#define SIFIVE_SPI_REG_SCKDIV 0x00 /* Serial clock divisor */
>> -#define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */
>> -#define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */
>> -#define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */
>> -#define SIFIVE_SPI_REG_CSMODE 0x18 /* Chip select mode */
>> -#define SIFIVE_SPI_REG_DELAY0 0x28 /* Delay control 0 */
>> -#define SIFIVE_SPI_REG_DELAY1 0x2c /* Delay control 1 */
>> -#define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */
>> -#define SIFIVE_SPI_REG_TXDATA 0x48 /* Tx FIFO data */
>> -#define SIFIVE_SPI_REG_RXDATA 0x4c /* Rx FIFO data */
>> -#define SIFIVE_SPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
>> -#define SIFIVE_SPI_REG_RXMARK 0x54 /* Rx FIFO watermark */
>> -#define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface
>> control */
>> -#define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction
>> format */
>> -#define SIFIVE_SPI_REG_IE 0x70 /* Interrupt Enable Register
>> */
>> -#define SIFIVE_SPI_REG_IP 0x74 /* Interrupt Pendings
>> Register */
>> -
>> -/* sckdiv bits */
>> -#define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU
>> -
>> -/* sckmode bits */
>> -#define SIFIVE_SPI_SCKMODE_PHA BIT(0)
>> -#define SIFIVE_SPI_SCKMODE_POL BIT(1)
>> -#define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA
>| \
>> - SIFIVE_SPI_SCKMODE_POL)
>> -
>> -/* csmode bits */
>> -#define SIFIVE_SPI_CSMODE_MODE_AUTO 0U
>> -#define SIFIVE_SPI_CSMODE_MODE_HOLD 2U
>> -#define SIFIVE_SPI_CSMODE_MODE_OFF 3U
>> -
>> -/* delay0 bits */
>> -#define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x))
>> -#define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU
>> -#define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16)
>> -#define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16)
>> -
>> -/* delay1 bits */
>> -#define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x))
>> -#define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU
>> -#define SIFIVE_SPI_DELAY1_INTERXFR(x) ((u32)(x) << 16)
>> -#define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16)
>> -
>> -/* fmt bits */
>> -#define SIFIVE_SPI_FMT_PROTO_SINGLE 0U
>> -#define SIFIVE_SPI_FMT_PROTO_DUAL 1U
>> -#define SIFIVE_SPI_FMT_PROTO_QUAD 2U
>> -#define SIFIVE_SPI_FMT_PROTO_MASK 3U
>> -#define SIFIVE_SPI_FMT_ENDIAN BIT(2)
>> -#define SIFIVE_SPI_FMT_DIR BIT(3)
>> -#define SIFIVE_SPI_FMT_LEN(x) ((u32)(x) << 16)
>> -#define SIFIVE_SPI_FMT_LEN_MASK (0xfU << 16)
>> -
>> -/* txdata bits */
>> -#define SIFIVE_SPI_TXDATA_DATA_MASK 0xffU
>> -#define SIFIVE_SPI_TXDATA_FULL BIT(31)
>> -
>> -/* rxdata bits */
>> -#define SIFIVE_SPI_RXDATA_DATA_MASK 0xffU
>> -#define SIFIVE_SPI_RXDATA_EMPTY BIT(31)
>> -
>> -/* ie and ip bits */
>> -#define SIFIVE_SPI_IP_TXWM BIT(0)
>> -#define SIFIVE_SPI_IP_RXWM BIT(1)
>> -
>> -struct sifive_spi {
>> - void *regs; /* base address of the registers */
>> - u32 fifo_depth;
>> - u32 bits_per_word;
>> - u32 cs_inactive; /* Level of the CS pins when
>> inactive*/
>> - u32 freq;
>> - u32 num_cs;
>> -};
>> +#include <asm/arch/spi.h>
>>
>> static void sifive_spi_prep_device(struct sifive_spi *spi,
>> struct dm_spi_slave_platdata
>> *slave)
>> --
>> 2.17.1
>>
>
>Overall, I don't like this unnecessary headers.
>
>Please drop this patch.
>
>We should add arch-fu540/xyz.h OR arch-sifive/xyz.h headers only if two
>different source files want to share define. Otherwise, it is always better to
>keep the register defines in driver source itself.
CCACHE_ENABLE used by fu540/ccache.h and in near future
U-boot cache driver will also use this.
GPIO_OUTPUT_VAL and GPIO_OUTPUT_EN register offsets used by spl.c and
drivers/gpio/sifive-gpio.c as well.
I don't want a duplicate copy for the same that's why I have added
arch-fu540 and arch-sifive.
Sifive specific values will be saved in arch-sifive and any SoC specific values
will
be saved in arch-SoC folder.
Let me know if you have any better suggestion to implement this.
>
>Regards,
>Anup
