Hi Mauro,
On 15.01.20 18:25, Mauro Condarelli wrote:
Note: I assumed u-boot-mtmips.bin is linked at 9c000000, right?
You don't need to know where it is linked to if you program it into
SPI NOR. But yes, the first stage the SPL is linked to 0x9c000000.
Can You elaborate, please?
Each image generated to boot from SPI NOR needs to be linked to 9c000000.
This is what the ROM image (non-RAM) of mainline does and the SPL image
of the dual image version (SPL plus main U-Boot proper) does.
I know for sure that if I flash at 30000 a u-boot that has been compiled
with SYS_TEXT_BASE = 0x9c000000 it will not start with "go 9c030000"
I need to rebuild with SYS_TEXT_BASE = 0x9c030000.
But you flash at offset 0 in SPI NOR, right? That's where the SoC starts
reading the bootloader binary after a reset or on power-up.
I was trying to say that, in my "secondary u-boot" attempts, where I
start from "paleolithic" and then do a "go <addr>" I need to put the
secondary at the same address specified in SYS_TEXT_BASE.
I mean:
if I want to boot directly from new then
SYS_TEXT_BASE = 0x9c000000
flash at start of SPI NOR
go 9c000000
else if I want to start "secondary" then
SYS_TEXT_BASE = 0x9c030000
flash at offset 30000 in SPI NOR
go 9c030000
Any other combination does not work (i.e.: I cannot flash and run at
start an u-boot compiled with SYS_TEXT_BASE = 0x9c030000 and
vice versa).
Note: I had to edit directly .config to change SYS_TEXT_BASE, apparently
it is visible in menuconfig only for ARM; am I missing something?
I can change it for my LinkIt target via "make menuconfig". Just search
for it by entering "/" in "make menuconfig" and it should show up there.
===8<------
I do have a led I can use for crude signalling, but I'm not really familiar
with mips Assembly.
Can You share the code to turn it on? (it is connected to
GPIO44/WLED(pin144).
i don't remember but it might be the case. Here the code snippet that
I used at that time. Perhaps it helps:
+#if 0 // test-only: WLAN LED on
+#define RALINK_SYSCTL_BASE 0xB0000000
+ // GPIO mode
+ li t0, RALINK_SYSCTL_BASE + 0x64
+ li t1, 0x05540551
+ sw t1, 0(t0)
+
+ // GPIO direction
+ li t0, RALINK_SYSCTL_BASE + 0x604
+ li t1, 0x00001000
+ sw t1, 0(t0)
+
+ // GPIO value
+ li t0, RALINK_SYSCTL_BASE + 0x624
+ li t1, 0x0002f5f
+ sw t1, 0(t0)
+#endif
Thanks,
Stefan
