>-----Original Message-----
>From: Joakim Tjernlund <joakim.tjernl...@infinera.com>
>Sent: Thursday, November 28, 2019 12:05 AM
>To: Priyanka Jain <priyanka.j...@nxp.com>; u-boot@lists.denx.de
>Cc: jo...@infinera.com <joakim.tjernl...@infinera.com>
>Subject: [PATCH] mpc85xx: ddr: Always start DDR RAM in Self Refresh mode
>
>Some of our t1042 boards fails DDR init with an Automatic calibration error
>every now and then. Investigations revealed that true Warm boots newer
>failed. Warm boots has some extra steps performed, one being to start DDRC
>in Self Refresh and then clearing SR right after.
>Applying this SR method unconditionally made all our boards stable again,
>regardless of Cold/Warm boot.
>
>Signed-off-by: Joakim Tjernlund <joakim.tjernl...@infinera.com>
>---
> drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 13 ++++++-------
> 1 file changed, 6 insertions(+), 7 deletions(-)
>
>diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
>b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
>index a9b085db8c..952b296dd8 100644
>--- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
>+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
>@@ -370,6 +370,8 @@ step2:
> debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr-
>>debug[2]));
>
> #endif /* part 1 of the workaound */
>+ /* Always start in self-refresh, clear after MEM_EN */
>+ setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
>
> /*
> * 500 painful micro-seconds must elapse between @@ -382,8 +384,6
>@@ step2:
>
> #ifdef CONFIG_DEEP_SLEEP
> if (is_warm_boot()) {
>- /* enter self-refresh */
>- setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
> /* do board specific memory setup */
> board_mem_sleep_setup();
> temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) |
>SDRAM_CFG_BI); @@ -395,6 +395,10 @@ step2:
> out_be32(&ddr->sdram_cfg, temp_sdram_cfg |
>SDRAM_CFG_MEM_EN);
> asm volatile("sync;isync");
>
>+ /* Exit self-refresh after DDR conf as some ddr memories can fail. */
>+ clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
>+ asm volatile("sync;isync");
>+
> total_gb_size_per_controller = 0;
> for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
> if (!(regs->cs[i].config & 0x80000000)) @@ -544,9 +548,4 @@
>step2:
> clrbits_be32(&ddr->sdram_cfg, 0x2);
> }
> #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */ -#ifdef
>CONFIG_DEEP_SLEEP
>- if (is_warm_boot())
>- /* exit self-refresh */
>- clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
>-#endif
> }
>--
>2.23.0
Patch applied on u-boot-mpc85xx. Awaiting upstream
Thanks Priyanka
