On Sat, Dec 7, 2019 at 12:54 PM Simon Glass <s...@chromium.org> wrote: > > Add code to init the system both in TPL and SPL. Each phase has its own > procedure. > > Signed-off-by: Simon Glass <s...@chromium.org> > --- > > Changes in v6: > - Change comment to apl_hostbridge_early_init_pinctrl, not apl_gpio_early_init > - Change commented-out enable_rtc_upper_bank() call to a TODO > - Make BOOT_FROM_FAST_SPI_FLASH a Kconfig option > - Rename init_for_uart() to board_debug_uart_init() > - Use SZ_4G instead of open-coded shift > > Changes in v5: None > Changes in v4: > - Switch over to use pinctrl for pad init/config > > Changes in v3: > - Adjust fast_spi_cache_bios_region() to avoid using SPI driver > - Drop calls to x86_cpu_init_f(), x86_cpu_reinit_f() > - Fix build error when debug UART is disabled > - Init the p2sb before the northbridge since the latter so it can use GPIOs > - Move location of fast_spi.h header file > - Shorten log_msg_ret() calls since the function name is always printed > - Support TPL without CONFIG_TPL_SPI_SUPPORT (reduces code size) > > Changes in v2: None > > arch/x86/cpu/apollolake/Makefile | 1 + > arch/x86/cpu/apollolake/cpu_spl.c | 271 ++++++++++++++++++++++++++++++ > 2 files changed, 272 insertions(+) > create mode 100644 arch/x86/cpu/apollolake/cpu_spl.c >
Reviewed-by: Bin Meng <bmeng...@gmail.com>
