Add board level support code for the SolidRun LX2160A based COM-Express
7 system.
Signed-off-by: Baruch Siach <bar...@tkos.co.il>
---
arch/arm/Kconfig | 13 +
arch/arm/cpu/armv8/Kconfig | 2 +-
board/solidrun/lx2160acex7/Kconfig | 15 ++
board/solidrun/lx2160acex7/MAINTAINERS | 7 +
board/solidrun/lx2160acex7/Makefile | 7 +
board/solidrun/lx2160acex7/README | 43 ++++
board/solidrun/lx2160acex7/lx2160acex7.c | 287 +++++++++++++++++++++++
configs/lx2160acex7_tfa_defconfig | 59 +++++
include/configs/lx2160acex7.h | 47 ++++
9 files changed, 479 insertions(+), 1 deletion(-)
create mode 100644 board/solidrun/lx2160acex7/Kconfig
create mode 100644 board/solidrun/lx2160acex7/MAINTAINERS
create mode 100644 board/solidrun/lx2160acex7/Makefile
create mode 100644 board/solidrun/lx2160acex7/README
create mode 100644 board/solidrun/lx2160acex7/lx2160acex7.c
create mode 100644 configs/lx2160acex7_tfa_defconfig
create mode 100644 include/configs/lx2160acex7.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f96841c77717..008af453987f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1201,6 +1201,18 @@ config TARGET_LX2160ARDB
is a high-performance development platform that supports the
QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
+config TARGET_LX2160ACEX7
+ bool "Support lx2160acex7"
+ select ARCH_LX2160A
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select ARCH_SUPPORT_TFABOOT
+ select BOARD_LATE_INIT
+ help
+ Support for SolidRun LX2160A based com express type 7 module and
+ platform. The lx2160acex7 high-performance platform that supports the
+ QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
+
config TARGET_LX2160AQDS
bool "Support lx2160aqds"
select ARCH_LX2160A
@@ -1821,6 +1833,7 @@ source "board/hisilicon/poplar/Kconfig"
source "board/isee/igep003x/Kconfig"
source "board/phytec/pcm051/Kconfig"
source "board/silica/pengwyn/Kconfig"
+source "board/solidrun/lx2160acex7/Kconfig"
source "board/spear/spear300/Kconfig"
source "board/spear/spear310/Kconfig"
source "board/spear/spear320/Kconfig"
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 92a2b58ed46d..9df6ebdc1bb4 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -109,7 +109,7 @@ config PSCI_RESET
!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
!TARGET_LS1046AFRWY && \
!TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
- !TARGET_LX2160AQDS && \
+ !TARGET_LX2160AQDS && !TARGET_LX2160ACEX7 && \
!ARCH_UNIPHIER && !TARGET_S32V234EVB
help
Most armv8 systems have PSCI support enabled in EL3, either through
diff --git a/board/solidrun/lx2160acex7/Kconfig
b/board/solidrun/lx2160acex7/Kconfig
new file mode 100644
index 000000000000..85673846a4a5
--- /dev/null
+++ b/board/solidrun/lx2160acex7/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LX2160ACEX7
+
+config SYS_BOARD
+ default "lx2160acex7"
+
+config SYS_VENDOR
+ default "solidrun"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "lx2160acex7"
+
+endif
diff --git a/board/solidrun/lx2160acex7/MAINTAINERS
b/board/solidrun/lx2160acex7/MAINTAINERS
new file mode 100644
index 000000000000..6fcc3dcc938c
--- /dev/null
+++ b/board/solidrun/lx2160acex7/MAINTAINERS
@@ -0,0 +1,7 @@
+LX2160ACEX7 BOARD
+M: Baruch Siach <bar...@tkos.co.il>
+S: Maintained
+F: board/solidrun/lx2160acex7/
+F: include/configs/lx2160acex7.h
+F: configs/lx2160acex7_tfa_defconfig
+F: arch/arm/dts/fsl-lx2160a-cex7.dts
diff --git a/board/solidrun/lx2160acex7/Makefile
b/board/solidrun/lx2160acex7/Makefile
new file mode 100644
index 000000000000..a2ee6fd8fde8
--- /dev/null
+++ b/board/solidrun/lx2160acex7/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2019 SolidRun ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += lx2160acex7.o
diff --git a/board/solidrun/lx2160acex7/README
b/board/solidrun/lx2160acex7/README
new file mode 100644
index 000000000000..33421073ad30
--- /dev/null
+++ b/board/solidrun/lx2160acex7/README
@@ -0,0 +1,43 @@
+Overview
+--------
+
+The SolidRun CEx7 LX2160A has COM-Express Type 7 form factor, based on NXP
+LX2160A SoC. SolidRun provides two carriers, Clearfog CX, and HoneyComb.
+
+https://developer.solid-run.com/products/cex7-lx2160a/
+
+U-Boot currentl supports boot from SD/eMMC.
+
+SD Boot Memory Map
+------------------
+
+Offsets are relative to the beginning of the SD card.
+
+0x001000 bl2_sd.pbl (RCW+PBI+bl2.pbl)
+0x100000 fip.bin (BL31 + BL33(U-Boot))
+0x500000 U-Boot Environment
+0x800000 DDR PHY Firmware (fip_ddr.bin)
+
+ATF (ARM Trusted Firmware) generates bl2_sd.pbl and fip.bin.
+
+fip_ddr.bin is available from https://github.com/NXP/ddr-phy-binary.
+
+DPAA2 Management Complex (MC) Firmware
+--------------------------------------
+
+U-Boot loads DPAA2 MC firmware and configuration files from the first SD/eMMC
+partition. The following environment variables define firmware files location.
+
+mc_firmware_dir : directory of firmware files
+mc_fw_file : MC firmware file name
+dpc_file : DPC file name
+dpl_file : DPL file name
+
+Default values for these variables are defined in
+include/configs/lx2160acex7.h.
+
+MC firmware is available from the linux-firmware repository at dpaa2/mc/.
+
+mc-utils generates DPL and DPC:
+
+ https://source.codeaurora.org/external/qoriq/qoriq-components/mc-utils
diff --git a/board/solidrun/lx2160acex7/lx2160acex7.c
b/board/solidrun/lx2160acex7/lx2160acex7.c
new file mode 100644
index 000000000000..57dd7605b7ee
--- /dev/null
+++ b/board/solidrun/lx2160acex7/lx2160acex7.c
@@ -0,0 +1,287 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 SolidRun ltd.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/platform_data/serial_pl01x.h>
+#include <netdev.h>
+#include <fsl_ddr.h>
+#include <fsl_sec.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <fsl-mc/fsl_mc.h>
+#include <asm/arch/soc.h>
+#include <fm_eth.h>
+#include <fsl-mc/ldpaa_wriop.h>
+#include <miiphy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pl01x_serial_platdata serial0 = {
+#if CONFIG_CONS_INDEX == 0
+ .base = CONFIG_SYS_SERIAL0,
+#elif CONFIG_CONS_INDEX == 1
+ .base = CONFIG_SYS_SERIAL1,
+#else
+#error "Unsupported console index value."
+#endif
+ .type = TYPE_PL011,
+};
+
+U_BOOT_DEVICE(nxp_serial0) = {
+ .name = "serial_pl01x",
+ .platdata = &serial0,
+};
+
+static struct pl01x_serial_platdata serial1 = {
+ .base = CONFIG_SYS_SERIAL1,
+ .type = TYPE_PL011,
+};
+
+U_BOOT_DEVICE(nxp_serial1) = {
+ .name = "serial_pl01x",
+ .platdata = &serial1,
+};
+
+static void uart_get_clock(void)
+{
+ serial0.clock = get_serial_clock();
+ serial1.clock = get_serial_clock();
+}
+
+int board_early_init_f(void)
+{
+ /* get required clock for UART IP */
+ uart_get_clock();
+ fsl_lsch3_early_init_f();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ enum boot_src src = get_boot_src();
+ char buf[64];
+ cpu_name(buf);
+ printf("Board: %s-CEX7, ", buf);
+
+ if (src == BOOT_SOURCE_SD_MMC) {
+ puts("SD\n");
+ }
+ puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 100MHz\n");
+ puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
+ puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
+ return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ return 100000000;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ return 100000000;
+}
+
+int board_init(void)
+{
+#ifdef CONFIG_FSL_CAAM
+ sec_init();
+#endif
+
+ return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+ int i;
+ u64 ddr_size = 0;
+
+ puts("\nDDR ");
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ ddr_size += gd->bd->bi_dram[i].size;
+ print_size(ddr_size, "");
+ print_ddr_info(0);
+}
+
+#ifdef CONFIG_FSL_MC_ENET
+void fdt_fixup_board_enet(void *fdt)
+{
+ int offset;
+
+ offset = fdt_path_offset(fdt, "/soc/fsl-mc");
+
+ if (offset < 0)
+ offset = fdt_path_offset(fdt, "/fsl-mc");
+
+ if (offset < 0) {
+ printf("%s: fsl-mc node not found in device tree (error %d)\n",
+ __func__, offset);
+ return;
+ }
+
+ if (get_mc_boot_status() == 0 &&
+ (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
+ fdt_status_okay(fdt, offset);
+ } else {
+ fdt_status_fail(fdt, offset);
+ }
+}
+
+void board_quiesce_devices(void)
+{
+ fsl_mc_ldpaa_exit(gd->bd);
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ int i;
+ bool mc_memory_bank = false;
+
+ u64 *base;
+ u64 *size;
+ u64 mc_memory_base = 0;
+ u64 mc_memory_size = 0;
+ u16 total_memory_banks;
+
+ ft_cpu_setup(blob, bd);
+
+ fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
+
+ if (mc_memory_base != 0)
+ mc_memory_bank = true;
+
+ total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+ base = calloc(total_memory_banks, sizeof(u64));
+ size = calloc(total_memory_banks, sizeof(u64));
+
+ /* fixup DT for the three GPP DDR banks */
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ base[i] = gd->bd->bi_dram[i].start;
+ size[i] = gd->bd->bi_dram[i].size;
+ }
+
+#ifdef CONFIG_RESV_RAM
+ /* reduce size if reserved memory is within this bank */
+ if (gd->arch.resv_ram >= base[0] &&
+ gd->arch.resv_ram < base[0] + size[0])
+ size[0] = gd->arch.resv_ram - base[0];
+ else if (gd->arch.resv_ram >= base[1] &&
+ gd->arch.resv_ram < base[1] + size[1])
+ size[1] = gd->arch.resv_ram - base[1];
+ else if (gd->arch.resv_ram >= base[2] &&
+ gd->arch.resv_ram < base[2] + size[2])
+ size[2] = gd->arch.resv_ram - base[2];
+#endif
+
+ if (mc_memory_base != 0) {
+ for (i = 0; i <= total_memory_banks; i++) {
+ if (base[i] == 0 && size[i] == 0) {
+ base[i] = mc_memory_base;
+ size[i] = mc_memory_size;
+ break;
+ }
+ }
+ }
+
+ fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
+
+#ifdef CONFIG_USB
+ fsl_fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_FSL_MC_ENET
+ fdt_fsl_mc_fixup_iommu_map_entry(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+
+ return 0;
+}
+#endif
+
+int fsl_initdram(void)
+{
+ gd->ram_size = tfa_get_dram_size();
+
+ if (!gd->ram_size)
+ gd->ram_size = fsl_ddr_sdram_size();
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FSL_MC_ENET)
+ struct memac_mdio_info mdio_info;
+ struct memac_mdio_controller *reg;
+ int i, interface;
+ struct mii_dev *dev;
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 srds_s1;
+
+ srds_s1 = in_le32(&gur->rcwsr[28]) &
+ FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+ reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ mdio_info.regs = reg;
+ mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
+
+ /* Register the EMI 1 */
+ fm_memac_mdio_init(bis, &mdio_info);
+
+ wriop_set_phy_address(WRIOP1_DPMAC17, 0,
+ RGMII_PHY_ADDR1);
+ reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ switch (srds_s1) {
+ case 3:
+ case 5:
+ case 8:
+ case 13:
+ case 14:
+ case 15:
+ case 17:
+ case 20:
+ case 23:
+ wriop_set_phy_address(WRIOP1_DPMAC17, 0,
+ RGMII_PHY_ADDR1);
+ break;
+
+ default:
+ printf("SerDes1 protocol 0x%x is not supported on
LX2160ACEX7\n",
+ srds_s1);
+ goto next;
+ }
+ for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC17; i++) {
+ interface = wriop_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
+ wriop_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+next:
+ cpu_eth_init(bis);
+#endif /* CONFIG_FSL_MC_ENET */
+
+ return pci_eth_init(bis);
+}
+
+void reset_phy(void)
+{
+#if defined(CONFIG_FSL_MC_ENET)
+ mc_env_boot();
+#endif
+}
diff --git a/configs/lx2160acex7_tfa_defconfig
b/configs/lx2160acex7_tfa_defconfig
new file mode 100644
index 000000000000..ee44d0693ac2
--- /dev/null
+++ b/configs/lx2160acex7_tfa_defconfig
@@ -0,0 +1,59 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LX2160ACEX7=y
+CONFIG_TFABOOT=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_F_LEN=0x6000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x500000
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CACHE=y
+CONFIG_MP=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-cex7"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SATA_CEVA=y
+CONFIG_FSL_CAAM=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_DM_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/include/configs/lx2160acex7.h b/include/configs/lx2160acex7.h
new file mode 100644
index 000000000000..5c1bd55aea3f
--- /dev/null
+++ b/include/configs/lx2160acex7.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 SolidRun ltd.
+ */
+
+#ifndef __LX2_CEX7_H
+#define __LX2_CEX7_H
+
+#include "lx2160a_common.h"
+
+/* MAC/PHY configuration */
+#if defined(CONFIG_FSL_MC_ENET)
+#define CONFIG_MII
+#define CONFIG_ETHPRIME "DPMAC17@rgmii-id"
+
+#define RGMII_PHY_ADDR1 0x01
+
+#endif
+
+#undef CONFIG_ID_EEPROM
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ EXTRA_ENV_SETTINGS \
+ "mc_firmware_dir=boot\0" \
+ "mc_fw_file=mc_lx2160a.itb\0" \
+ "mc_fw_addr=0x80a00000\0" \
+ "dpc_file=dpc-8_x_usxgmii.dtb\0" \
+ "dpc_addr=0x80e00000\0" \
+ "dpl_file=dpl-eth.8x10g.19.dtb\0" \
+ "dpl_addr=0x80d00000\0"
+
+#undef SD_MC_INIT_CMD
+#define SD_MC_INIT_CMD \
+ "load mmc 0:1 ${mc_fw_addr} ${mc_firmware_dir}/${mc_fw_file}; " \
+ "load mmc 0:1 ${dpc_addr} ${mc_firmware_dir}/${dpc_file}; " \
+ "fsl_mc start mc ${mc_fw_addr} ${dpc_addr}\0"
+
+#undef SD_BOOTCOMMAND
+#define SD_BOOTCOMMAND \
+ "load mmc 0:1 ${dpl_addr} ${mc_firmware_dir}/${dpl_file}; " \
+ "fsl_mc lazyapply dpl ${dpl_addr}; " \
+ "run distro_bootcmd"
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LX2_CEX7_H */
--
2.24.0
