On Mon, Dec 2, 2019 at 11:25 AM <chee.hong....@intel.com> wrote: > > From: "Ang, Chee Hong" <chee.hong....@intel.com> > > New U-boot flow with ARM Trusted Firmware (ATF) support: > SPL (EL3) -> ATF-BL31 (EL3) -> U-Boot Proper (EL2) -> Linux (EL1)
Adding support for ATF means that using U-Boot on Stratix10 and Agilex without ATF keeps working, right? > > SPL loads the u-boot.itb which consist of: > 1) u-boot-nodtb.bin (U-Boot Proper image) > 2) u-boot.dtb (U-Boot Proper DTB) > 3) bl31.bin (ATF-BL31 image) > > Supported Platform: Intel SoCFPGA 64bits (Stratix10 & Agilex) > > Now, U-Boot Proper is running in non-secure mode (EL2), it invokes > SMC/PSCI calls provided by ATF to perform COLD reset, System Manager > register accesses and mailbox communications with Secure Device Manager > (SDM). > > Steps to build the U-Boot with ATF support: > 1) Build U-Boot > 2) Build ATF BL31 > 3) Copy ATF BL31 binary image into U-Boot's root folder > 4) "make u-boot.itb" to generate u-boot.itb > > These patchsets have dependency on: > [U-Boot,v8,00/19] Add Intel Agilex SoC support: > https://patchwork.ozlabs.org/cover/1201373/ > > Chee Hong Ang (19): > arm: socfpga: add fit source file for pack itb with ATF > arm: socfpga: Add function for checking description from FIT image > arm: socfpga: Load FIT image with ATF support > arm: socfpga: Override 'lowlevel_init' to support ATF > configs: socfpga: Enable FIT image loading with ATF support > arm: socfpga: Disable "spin-table" method for booting Linux > arm: socfpga: Add SMC helper function for Intel SOCFPGA (64bits) > arm: socfpga: Define SMC function identifiers for PSCI SiP services > arm: socfpga: Add secure register access helper functions for SoC > 64bits > arm: socfpga: Secure register access for clock manager (SoC 64bits) > arm: socfpga: Secure register access in PHY mode setup > arm: socfpga: Secure register access for reading PLL frequency > mmc: dwmmc: socfpga: Secure register access in MMC driver > net: designware: socfpga: Secure register access in MAC driver > arm: socfpga: Secure register access in Reset Manager driver > arm: socfpga: stratix10: Initialize timer in SPL > arm: socfpga: stratix10: Refactor FPGA reconfig driver to support ATF > arm: socfpga: Bridge reset now invokes SMC calls to query FPGA config > status > sysreset: socfpga: Invoke PSCI call for COLD reset > > Dalon Westergreen (1): > configs: stratix10: Remove CONFIG_OF_EMBED This one is included in another series already: https://patchwork.ozlabs.org/user/todo/uboot/?series=132976 Does this mean that one will be abandonen? So the combined hex output part of that series is not required any more? Regards, Simon > > arch/arm/mach-socfpga/Kconfig | 2 - > arch/arm/mach-socfpga/Makefile | 4 + > arch/arm/mach-socfpga/board.c | 10 + > arch/arm/mach-socfpga/clock_manager_agilex.c | 5 +- > arch/arm/mach-socfpga/clock_manager_s10.c | 5 +- > arch/arm/mach-socfpga/include/mach/misc.h | 3 + > .../mach-socfpga/include/mach/secure_reg_helper.h | 20 ++ > arch/arm/mach-socfpga/lowlevel_init.S | 48 +++ > arch/arm/mach-socfpga/misc_s10.c | 47 ++- > arch/arm/mach-socfpga/reset_manager_s10.c | 31 +- > arch/arm/mach-socfpga/secure_reg_helper.c | 67 ++++ > arch/arm/mach-socfpga/timer_s10.c | 3 +- > arch/arm/mach-socfpga/wrap_pll_config_s10.c | 9 +- > board/altera/soc64/its/fit_spl_atf.its | 51 +++ > configs/socfpga_agilex_defconfig | 8 +- > configs/socfpga_stratix10_defconfig | 9 +- > drivers/fpga/stratix10.c | 261 ++++---------- > drivers/mmc/socfpga_dw_mmc.c | 7 +- > drivers/net/dwmac_socfpga.c | 5 +- > drivers/sysreset/sysreset_socfpga_s10.c | 4 +- > include/configs/socfpga_soc64_common.h | 2 +- > include/linux/intel-smc.h | 374 > +++++++++++++++++++++ > 22 files changed, 732 insertions(+), 243 deletions(-) > create mode 100644 arch/arm/mach-socfpga/include/mach/secure_reg_helper.h > create mode 100644 arch/arm/mach-socfpga/lowlevel_init.S > create mode 100644 arch/arm/mach-socfpga/secure_reg_helper.c > create mode 100644 board/altera/soc64/its/fit_spl_atf.its > create mode 100644 include/linux/intel-smc.h > > -- > 2.7.4 > _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
