On Mon, Nov 25, 2019 at 12:11 PM Simon Glass <s...@chromium.org> wrote: > > Newer Intel SoCs have different ways of setting up cache-as-ram (CAR). > Add support for these along with suitable configuration options. > > To make the code cleaner, adjust a few definitions in processor.h so that > they can be used from assembler. > > Signed-off-by: Simon Glass <s...@chromium.org> > --- > > Changes in v5: None > Changes in v4: > - Adjust > - Fix up license header > - Fix various code-style problems > - Use CONFIG_INTEL_CAR_CQOS to control car2.S inclusion > - Use car_init_ret to return > - Use post_code() calls consistent with car.S > > Changes in v3: > - Drop dead code > - Drop unneeded Kconfig file > - Use a macro for is-power-of-two > > Changes in v2: None > > arch/x86/Kconfig | 16 + > arch/x86/cpu/intel_common/Makefile | 8 + > arch/x86/cpu/intel_common/car2.S | 448 ++++++++++++++++++++++++ > arch/x86/cpu/intel_common/car2_uninit.S | 87 +++++ > arch/x86/include/asm/processor.h | 12 +- > 5 files changed, 564 insertions(+), 7 deletions(-) > create mode 100644 arch/x86/cpu/intel_common/car2.S > create mode 100644 arch/x86/cpu/intel_common/car2_uninit.S >
Reviewed-by: Bin Meng <bmeng...@gmail.com> _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
