Add new FPGA ID for ArriaV ST/D3 or SX/B3 .
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chin Liang See <chin.liang....@intel.com>
Cc: Dalon Westergreen <dwest...@gmail.com>
Cc: Dinh Nguyen <dingu...@kernel.org>
Cc: Ley Foon Tan <ley.foon....@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschm...@gmail.com>
Cc: Tien Fong Chee <tien.fong.c...@intel.com>
---
arch/arm/mach-socfpga/misc_gen5.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc_gen5.c
b/arch/arm/mach-socfpga/misc_gen5.c
index 65d3485bc5..22042d0de0 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -79,6 +79,8 @@ static const struct {
{ 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" },
/* Arria V */
{ 0x2d03, "Arria V, D5", "av_d5" },
+ /* Arria V ST/SX */
+ { 0x2d13, "Arria V, ST/D3 or SX/B3", "av_st_d3" },
};
static int socfpga_fpga_id(const bool print_id)
--
2.24.0.432.g9d3f5f5b63
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