On Thu, Nov 14, 2019 at 3:49 AM Simon Goldschmidt <simon.k.r.goldschm...@gmail.com> wrote: > > Am 08.11.2019 um 05:11 schrieb Ley Foon Tan: > > Add build support for Agilex SoC. > > > > Signed-off-by: Ley Foon Tan <ley.foon....@intel.com> > > Reviewed-by: Simon Goldschmidt <simon.k.r.goldschm...@gmail.com> > > > > --- > > v6: > > - Include socfpga_soc64_common.h. > > > > v5: > > - Enable NCORE_CACHE > > > > v3: > > - Disable CONFIG_USE_TINY_PRINTF > > > > v2: > > - Remove IC_CLK define, use clock DM method to get i2c clock > > - Change CONFIG_ENV_SIZE to 4KB since CONFIG_SPI_FLASH_USE_4K_SECTORS is > > enabled. > > --- > > arch/arm/Kconfig | 4 +- > > arch/arm/mach-socfpga/Kconfig | 16 +++++++ > > arch/arm/mach-socfpga/Makefile | 9 ++++ > > configs/socfpga_agilex_defconfig | 58 ++++++++++++++++++++++++++ > > include/configs/socfpga_agilex_socdk.h | 15 +++++++ > > 5 files changed, 100 insertions(+), 2 deletions(-) > > create mode 100644 configs/socfpga_agilex_defconfig > > create mode 100644 include/configs/socfpga_agilex_socdk.h > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > index 629c5e8c2d..723bd5c619 100644 > > --- a/arch/arm/Kconfig > > +++ b/arch/arm/Kconfig > > @@ -905,7 +905,7 @@ config ARCH_SOCFPGA > > bool "Altera SOCFPGA family" > > select ARCH_EARLY_INIT_R > > select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10 > > - select ARM64 if TARGET_SOCFPGA_STRATIX10 > > + select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX > > select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 > > select DM > > select DM_SERIAL > > @@ -917,7 +917,7 @@ config ARCH_SOCFPGA > > select SPL_LIBGENERIC_SUPPORT > > select SPL_NAND_SUPPORT if SPL_NAND_DENALI > > select SPL_OF_CONTROL > > - select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 > > + select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || > > TARGET_SOCFPGA_AGILEX > > select SPL_SERIAL_SUPPORT > > select SPL_SYSRESET > > select SPL_WATCHDOG_SUPPORT > > diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig > > index fc0a54214f..922442a31f 100644 > > --- a/arch/arm/mach-socfpga/Kconfig > > +++ b/arch/arm/mach-socfpga/Kconfig > > @@ -26,6 +26,15 @@ config SYS_TEXT_BASE > > default 0x01000040 if TARGET_SOCFPGA_ARRIA10 > > default 0x01000040 if TARGET_SOCFPGA_GEN5 > > > > +config TARGET_SOCFPGA_AGILEX > > + bool > > + select ARMV8_MULTIENTRY > > + select ARMV8_SET_SMPEN > > + select ARMV8_SPIN_TABLE > > + select CLK > > + select NCORE_CACHE > > + select SPL_CLK if SPL > > + > > config TARGET_SOCFPGA_ARRIA5 > > bool > > select TARGET_SOCFPGA_GEN5 > > @@ -72,6 +81,10 @@ choice > > prompt "Altera SOCFPGA board select" > > optional > > > > +config TARGET_SOCFPGA_AGILEX_SOCDK > > + bool "Intel SOCFPGA SoCDK (Agilex)" > > + select TARGET_SOCFPGA_AGILEX > > + > > config TARGET_SOCFPGA_ARIES_MCVEVK > > bool "Aries MCVEVK (Cyclone V)" > > select TARGET_SOCFPGA_CYCLONE5 > > @@ -132,6 +145,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT > > endchoice > > > > config SYS_BOARD > > + default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK > > default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK > > default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK > > default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK > > @@ -148,6 +162,7 @@ config SYS_BOARD > > default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA > > > > config SYS_VENDOR > > + default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK > > default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK > > default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK > > default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK > > @@ -165,6 +180,7 @@ config SYS_SOC > > default "socfpga" > > > > config SYS_CONFIG_NAME > > + default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK > > default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK > > default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK > > default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK > > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile > > index 81b6ffc675..418f543b20 100644 > > --- a/arch/arm/mach-socfpga/Makefile > > +++ b/arch/arm/mach-socfpga/Makefile > > @@ -41,6 +41,14 @@ endif > > > > ifdef CONFIG_TARGET_SOCFPGA_AGILEX > > obj-y += clock_manager_agilex.o > > +obj-y += mailbox_s10.o > > +obj-y += misc_s10.o > > +obj-y += mmu-arm64_s10.o > > +obj-y += reset_manager_s10.o > > +obj-y += system_manager_s10.o > > +obj-y += timer_s10.o > > +obj-y += wrap_pinmux_config_s10.o > > +obj-y += wrap_pll_config_s10.o > > endif > > > > ifdef CONFIG_SPL_BUILD > > @@ -59,6 +67,7 @@ obj-y += firewall.o > > obj-y += spl_s10.o > > endif > > ifdef CONFIG_TARGET_SOCFPGA_AGILEX > > +obj-y += firewall.o > > obj-y += spl_agilex.o > > endif > > endif > > diff --git a/configs/socfpga_agilex_defconfig > > b/configs/socfpga_agilex_defconfig > > new file mode 100644 > > index 0000000000..c221500155 > > --- /dev/null > > +++ b/configs/socfpga_agilex_defconfig > > @@ -0,0 +1,58 @@ > > +CONFIG_ARM=y > > +CONFIG_ARCH_SOCFPGA=y > > +CONFIG_SYS_TEXT_BASE=0x1000 > > +CONFIG_SYS_MALLOC_F_LEN=0x2000 > > +CONFIG_NR_DRAM_BANKS=2 > > +CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y > > +CONFIG_IDENT_STRING="socfpga_agilex" > > +CONFIG_SPL_FS_FAT=y > > +CONFIG_SPL_TEXT_BASE=0xFFE00000 > > +CONFIG_BOOTDELAY=5 > > +CONFIG_SPL_CACHE=y > > +CONFIG_SPL_SPI_LOAD=y > > +CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c00000 > > +CONFIG_HUSH_PARSER=y > > +CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " > > +CONFIG_CMD_MEMTEST=y > > +# CONFIG_CMD_FLASH is not set > > +CONFIG_CMD_GPIO=y > > +CONFIG_CMD_I2C=y > > +CONFIG_CMD_MMC=y > > +CONFIG_CMD_SPI=y > > +CONFIG_CMD_USB=y > > +CONFIG_CMD_DHCP=y > > +CONFIG_CMD_MII=y > > +CONFIG_CMD_PING=y > > +CONFIG_CMD_CACHE=y > > +CONFIG_CMD_EXT4=y > > +CONFIG_CMD_FAT=y > > +CONFIG_CMD_FS_GENERIC=y > > +CONFIG_OF_EMBED=y > > +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" > > +CONFIG_ENV_IS_IN_MMC=y > > +CONFIG_NET_RANDOM_ETHADDR=y > > +CONFIG_SPL_DM_SEQ_ALIAS=y > > +CONFIG_SPL_ALTERA_SDRAM=y > > +CONFIG_DM_GPIO=y > > +CONFIG_DWAPB_GPIO=y > > +CONFIG_DM_I2C=y > > +CONFIG_SYS_I2C_DW=y > > +CONFIG_DM_MMC=y > > +CONFIG_MMC_DW=y > > +CONFIG_SF_DEFAULT_MODE=0x2003 > > +CONFIG_SPI_FLASH_SPANSION=y > > +CONFIG_SPI_FLASH_STMICRO=y > > +CONFIG_PHY_MICREL=y > > +CONFIG_PHY_MICREL_KSZ90X1=y > > +CONFIG_DM_ETH=y > > +CONFIG_ETH_DESIGNWARE=y > > +CONFIG_MII=y > > +CONFIG_DM_RESET=y > > +CONFIG_SPI=y > > +CONFIG_CADENCE_QSPI=y > > +CONFIG_DESIGNWARE_SPI=y > > +CONFIG_USB=y > > +CONFIG_DM_USB=y > > +CONFIG_USB_DWC2=y > > +CONFIG_USB_STORAGE=y > > +# CONFIG_SPL_USE_TINY_PRINTF is not set > > diff --git a/include/configs/socfpga_agilex_socdk.h > > b/include/configs/socfpga_agilex_socdk.h > > new file mode 100644 > > index 0000000000..7d6625099c > > --- /dev/null > > +++ b/include/configs/socfpga_agilex_socdk.h > > @@ -0,0 +1,15 @@ > > +/* SPDX-License-Identifier: GPL-2.0 > > + * > > + * Copyright (C) 2019 Intel Corporation <www.intel.com> > > + * > > + */ > > + > > +#ifndef __CONFIG_SOCFGPA_AGILEX_H__ > > +#define __CONFIG_SOCFGPA_AGILEX_H__ > > + > > +#include <configs/socfpga_soc64_common.h> > > + > > +#undef CONFIG_DW_WDT_CLOCK_KHZ > > +#define CONFIG_DW_WDT_CLOCK_KHZ 100000 > > Can you move this definition up three lines and do something like > "#ifndef ..." in socfpga_soc64_common.h? > Okay.
Thanks. Regards Ley Foon _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
