[U-Boot] [RFC PATCH v3 2/3] arm: dts: ls1028a: add node for the integrated Ethernet switch

[Alex Marginean]

Adds a device tree node to ls1028a dtsi that describes the Ethernet switch
integrated in LS1028A SoC.

Signed-off-by: Alex Marginean <alexandru.margin...@nxp.com>
---
 arch/arm/dts/fsl-ls1028a-rdb.dts | 36 ++++++++++++++++++++++++++++++++
 arch/arm/dts/fsl-ls1028a.dtsi    | 31 +++++++++++++++++++++++++++
 2 files changed, 67 insertions(+)

diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts
index 3d5e8ade21..e1e8e135e2 100644
--- a/arch/arm/dts/fsl-ls1028a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1028a-rdb.dts
@@ -114,9 +114,45 @@
        phy-handle = <&rdb_phy0>;
 };
 
+&ethsw {
+       port@0 {
+               status = "okay";
+               phy-mode = "qsgmii";
+               phy-handle = <&sw_phy0>;
+       };
+       port@1 {
+               status = "okay";
+               phy-mode = "qsgmii";
+               phy-handle = <&sw_phy1>;
+       };
+       port@2 {
+               status = "okay";
+               phy-mode = "qsgmii";
+               phy-handle = <&sw_phy2>;
+       };
+       port@3 {
+               status = "okay";
+               phy-mode = "qsgmii";
+               phy-handle = <&sw_phy3>;
+       };
+};
+
 &mdio0 {
        status = "okay";
        rdb_phy0: phy@2 {
                reg = <2>;
        };
+
+       sw_phy0: phy@10 {
+               reg = <0x10>;
+       };
+       sw_phy1: phy@11 {
+               reg = <0x11>;
+       };
+       sw_phy2: phy@12 {
+               reg = <0x12>;
+       };
+       sw_phy3: phy@13 {
+               reg = <0x13>;
+       };
 };
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 43a154e8e7..21595713df 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -136,6 +136,37 @@
                        reg = <0x000300 0 0 0 0>;
                        status = "disabled";
                };
+               ethsw: pci@0,5 {
+                       #address-cells=<0>;
+                       #size-cells=<1>;
+                       reg = <0x000500 0 0 0 0>;
+                       port@0 {
+                               reg = <0>;
+                               status = "disabled";
+                       };
+                       port@1 {
+                               reg = <1>;
+                               status = "disabled";
+                       };
+                       port@2 {
+                               reg = <2>;
+                               status = "disabled";
+                       };
+                       port@3 {
+                               reg = <3>;
+                               status = "disabled";
+                       };
+                       port@4 {
+                               reg = <4>;
+                               phy-mode = "internal";
+                               status = "okay";
+                       };
+                       port@5 {
+                               reg = <5>;
+                               phy-mode = "internal";
+                               status = "okay";
+                       };
+               };
                enetc6: pci@0,6 {
                        reg = <0x000600 0 0 0 0>;
                        status = "okay";
-- 
2.17.1

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