On 2019/10/25 下午3:47, Heiko Stübner wrote:
Hi Kever,
Am Freitag, 25. Oktober 2019, 04:49:54 CEST schrieb Kever Yang:
On 2019/10/25 上午7:28, Heiko Stuebner wrote:
From: Kever Yang <kever.y...@rock-chips.com>
Add core architecture code to support the px30 soc.
This includes a separate tpl board file due to very limited
sram size as well as a non-dm sdram driver, as this also has
to fit into the tiny sram.
Could you leave the sram code and make it possible to use the common
sdram code
I have send out:
https://patchwork.ozlabs.org/cover/1183700/
The sram driver should goes to driver/ram folder instead of arch/arm folder.
That won't work. For the px30, the ddr-init portion will need to stay in
arch-rockchip/px30 I'm afraid.
To compile things in drivers/ram you need to have TPL_RAM enabled
which in turn depends on TPL_DM which in turn makes the tpl size
to big.
Can we just update the TPL_RAM not depends on DM, and leave the code in
the driver/ram folder,
and let the code itself to decide if use DM or not? We do use
CONFIG_TPL_BUILD and CONFIG_SPL_BUILD
for dram driver code to make choice.
The core implement of PX30 DRAM driver is shared with other SoCs, it
should be at the same place with
other SoCs.
Thanks,
- Kever
So drivers/ram/... can probably only contain the dm-based part I introduce
in patch9 of this series.
Heiko
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